Jaan Raik - RankMe

250 papers A 11B 16C 65Misc 7Journal 60Unranked 88

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Progressive Training of Hybrid Clipped Rectified Linear Unit for Resilient Convolution Neural Networks. IEEE Access Seyedhamidreza Mousavi, Mohammad Hasan Ahmadilivani, Jaan Raik, Maksim Jenihhin, Masoud Daneshtalab
2026	J	`jnl`	RSCAAT: A Recursive Mechanism to Mitigate Cache Side Channel Attacks. IEEE Access Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik
2026	—	`conf`	Reliability Assessment of Deep Neural Networks and Accelerators Across Design Stages. LATS Mohammad Hasan Ahmadilivani, Natalia Cherezova, Michael Glaß, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Letícia Maria Veiras Bolzani Poehls, Jaan Raik, Lucas Roquet, Fernando Fernandes dos Santos, Felipe Augusto da Silva, Matteo Sonza Reorda, Alessandro Veronesi, Ernesto Cristopher Villegas Castillo, Josie E. Rodriguez Condia
2025	J	`jnl`	DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining. CoRR Muhammad Hassan, Maria Mushtaq, Jaan Raik, Tara Ghasempouri
2025	—	`conf`	Does Fault Tolerance Safeguard DNNs Against Bitfiip Attacks? A Case Study. DFT Mohammad Hasan Ahmadilivani, Yuto Kobayashi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	J	`jnl`	SAFFIRA A Framework for Assessing the Reliability of Systolic-Array DNN Accelerators. J. Circuits Syst. Comput. Salvatore Pappalardo, Nicolò Bellarmino, Bastien Deveautour, Alberto Bosio, Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2025	—	`conf`	Special Session Paper: Application of Functional Verification Techniques in Hardware Trust. DFT Mohammad Reza Heidari Iman, Rolf Drechsler, Chandan Kumar Jha, Ali Azarpeyvand, Tara Ghasempouri, Sharjeel Imtiaz, Jaan Raik, Samuele Germiniani, Daniele Nicoletti, Graziano Pravadelli, Giorgio Di Natale
2025	—	`conf`	SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions. ISVLSI Ali Azarpeyvand, Mohammad Eslami, Gert Jervan, Jaan Raik, Tara Ghasempouri
2024	J	`jnl`	A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. ACM Comput. Surv. Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	A	`conf`	ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms. DATE Andrew Roberts, Mohammad Reza Heidari Iman, Mauro Bellone, Tara Ghasempouri, Jaan Raik, Olaf Maennel, Mohammad Hamad, Sebastian Steinhorst
2024	B	`conf`	AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. ETS Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2024	J	`jnl`	AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. CoRR Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2024	C	`conf`	Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. IOLTS Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	J	`jnl`	Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. CoRR Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	J	`jnl`	DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network. CoRR Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	—	`conf`	Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. ISQED Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik
2024	J	`jnl`	Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. CoRR Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik
2024	C	`conf`	Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. VLSI-SoC Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin
2024	—	`conf`	Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
2024	J	`jnl`	ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs. CoRR Seyedhamidreza Mousavi, Mohammad Hasan Ahmadilivani, Jaan Raik, Maksim Jenihhin, Masoud Daneshtalab
2024	C	`conf`	SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. DDECS Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio
2024	J	`jnl`	SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. CoRR Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio
2024	—	`conf`	Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs. DFT Hardi Selg, Konstantin Shibin, Anton Tsertov, Maksim Jenihhin, Peeter Ellervee, Jaan Raik
2024	Misc	`conf`	Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola
2024	—	`book`	Structural Decision Diagrams in Digital Test - Theory and Applications Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman
2024	J	`jnl`	Survey on Architectural Attacks: A Unified Classification and Attack Model. ACM Comput. Surv. Tara Ghasempouri, Jaan Raik, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil
2024	—	`conf`	Zero-Memory-Overhead Clipping-Based Fault Tolerance for LSTM Deep Neural Networks. DFT Bahram Parchekani, Samira Nazari, Mohammad Hasan Ahmadilivani, Ali Azarpeyvand, Jaan Raik, Tara Ghasempouri, Masoud Daneshtalab
2023	C	`ed.`	26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023 DDECS Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek
2023	J	`jnl`	A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. CoRR Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	C	`conf`	APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. DDECS Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik
2023	J	`jnl`	APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. CoRR Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik
2023	—	`conf`	Adaptive Kalman Filter Based Data Aggregation in Fault-Resilient Underwater Sensor Networks. DSP Lauri Vihman, Jaan Raik
2023	J	`jnl`	An automated method for mining high-quality assertion sets. Microprocess. Microsystems Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri
2023	—	`conf`	Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks. DFT Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab, Alar Kuusik
2023	—	`conf`	DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. ISQED Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper
2023	J	`jnl`	DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. CoRR Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper
2023	B	`conf`	DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. ETS Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	J	`jnl`	DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment. CoRR Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	—	`conf`	Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. AICAS Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	J	`jnl`	Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. CoRR Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	—	`conf`	Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation. ICECS Iman Dadras, Sakineh Seydi, Mohammad Hasan Ahmadilivani, Jaan Raik, Mostafa E. Salehi
2023	J	`jnl`	Hybrid Protection of Digital FIR Filters. CoRR Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2023	J	`jnl`	Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2023	C	`conf`	ML-Based Online Design Error Localization for RISC-V Implementations. IOLTS Hardi Selg, Maksim Jenihhin, Peeter Ellervee, Jaan Raik
2023	Misc	`conf`	Special Session: Approximation and Fault Resiliency of DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri
2023	J	`jnl`	Special Session: Approximation and Fault Resiliency of DNN Accelerators. CoRR Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri
2022	—	`conf`	An Efficient Analog Convolutional Neural Network Hardware Accelerator Enabled by a Novel Memoryless Architecture for Insect-Sized Robots. MOCAST Iman Dadras, Mohammad Hasan Ahmadilivani, Saoni Banerji, Jaan Raik, Alvo Aabloo
2022	—	`conf`	High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2022	C	`conf`	IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets. DSD Mohammad Reza Heidari Iman, Jaan Raik, Gert Jervan, Tara Ghasempouri
2022	J	`jnl`	Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study. IEEE Access Felipe Almeida, Malik Imran, Jaan Raik, Samuel Pagliarini
2022	J	`jnl`	Survey on Architectural Attacks: A Unified Classification and Attack Model. CoRR Tara Ghasempouri, Jaan Raik, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil
2021	—	`conf`	A Methodology for Automated Mining of Compact and Accurate Assertion Sets. NorCAS Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri
2021	C	`conf`	CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector. DDECS Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik
2021	—	`conf`	Design Space Exploration of SABER in 65nm ASIC. ASHES@CCS Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini
2021	J	`jnl`	Design Space Exploration of SABER in 65nm ASIC. CoRR Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini
2021	J	`jnl`	Design Space Exploration of SABER in 65nm ASIC. IACR Cryptol. ePrint Arch. Malik Imran, Felipe Almeida, Jaan Raik, Andrea Basso, Sujoy Sinha Roy, Samuel Pagliarini
2021	C	`conf`	High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2021	J	`jnl`	High-level Intellectual Property Obfuscation via Decoy Constants. CoRR Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2021	C	`conf`	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar
2021	—	`conf`	Side-Channel Attacks on Triple Modular Redundancy Schemes. ATS Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini
2021	J	`jnl`	Side-Channel Attacks on Triple Modular Redundancy Schemes. CoRR Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini
2021	J	`jnl`	Systematic Review of Fault Tolerant Techniques in Underwater Sensor Networks. Sensors Lauri Vihman, Maarja Kruusmaa, Jaan Raik
2021	A	`conf`	Triple Fixed-Point MAC Unit for Deep Learning. DATE Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein
2020	C	`conf`	A Security Verification Template to Assess Cache Architecture Vulnerabilities. DDECS Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil
2020	J	`jnl`	Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. CoRR Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2020	C	`conf`	Adjustable self-healing methodology for accelerated functions in heterogeneous systems. DSD Mohammad Riazati, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper
2020	Misc	`conf`	An Efficient FPGA-based Architecture for Contractive Autoencoders. FCCM Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein
2020	J	`jnl`	Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	Misc	`conf`	Data-Driven Cross-Layer Fault Management Architecture for Sensor Networks. EDCC Lauri Vihman, Maarja Kruusmaa, Jaan Raik
2020	J	`jnl`	Efficient Fault Injection based on Dynamic HDL Slicing Technique. CoRR Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2020	J	`jnl`	High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	C	`conf`	Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	B	`conf`	LiD-CAT: A Lightweight Detector for Cache ATtacks. ETS Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil, Behrad Niazmand, Tara Ghasempouri, Jaan Raik, Johanna Sepúlveda
2020	—	`conf`	NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad. ISVLSI Ameer Shalabi, Kolin Paul, Tara Ghasempouri, Jaan Raik
2020	J	`jnl`	New categories of Safe Faults in a processor-based Embedded System. CoRR Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2020	J	`jnl`	PASCAL: Timing SCA Resistant Design and Verification Flow. CoRR Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
2020	A	`conf`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2020	C	`conf`	SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks. DSD Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik
2019	—	`conf`	Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. NORCAS Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2019	—	`conf`	An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
2019	C	`conf`	Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran
2019	C	`conf`	Efficient Fault Injection based on Dynamic HDL Slicing Technique. IOLTS Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2019	C	`conf`	Engineering of an Effective Automatic Dynamic Assertion Mining Platform. VLSI-SoC Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik
2019	C	`conf`	Fault-Aware Performance Assessment Approach for Embedded Networks. DDECS Jan Malburg, Karl Janson, Jaan Raik, Frank Dannemann
2019	B	`conf`	High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	J	`jnl`	High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	A	`conf`	IEEE European Test Symposium (ETS). ITC Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu
2019	C	`conf`	Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2019	—	`conf`	Mixed-level identification of fault redundancy in microprocessors. LATS Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	J	`jnl`	Mixed-level identification of fault redundancy in microprocessors. CoRR Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	C	`conf`	New categories of Safe Faults in a processor-based Embedded System. DDECS Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2019	—	`conf`	On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2019	J	`jnl`	Overview of Fault Tolerant Techniques in Underwater Sensor Networks. CoRR Lauri Vihman, Maarja Kruusmaa, Jaan Raik
2019	C	`conf`	PASCAL: Timing SCA Resistant Design and Verification Flow. IOLTS Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
2019	J	`jnl`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019	C	`conf`	RTL Assertion Mining with Automated RTL-to-TLM Abstraction. FDL Tara Ghasempouri, Alessandro Danese, Graziano Pravadelli, Nicola Bombieri, Jaan Raik
2019	—	`conf`	Software-Based Mitigation for Memory Address Decoder Aging. LATS Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui
2019	J	`jnl`	Towards Multidimensional Verification: Where Functional Meets Non-Functional. CoRR Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
2019	J	`jnl`	Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu
2018	—	`conf`	A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers. ITC-Asia Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan
2018	—	`conf`	AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. ReCoSoC Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
2018	—	`conf`	An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics. ITC-Asia Tara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik
2018	C	`conf`	Design Understanding: From Logic to Specification VLSI-SoC Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener
2018	J	`jnl`	Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
2018	—	`conf`	From RTL Liveness Assertions to Cost-Effective Hardware Checkers. DCIS Ranganathan Hariharan, Tara Ghasempouri, Behrad Niazmand, Jaan Raik
2018	—	`conf`	Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
2018	—	`conf`	Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
2018	C	`conf`	QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. DDECS Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
2018	C	`conf`	Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling. IOLTS Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto García Ortiz, Rolf Drechsler
2018	C	`conf`	Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey
2018	—	`conf`	Timing-critical path analysis with structurally synthesized BDDs. MECO Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
2018	—	`conf`	Towards Multidimensional Verification: Where Functional Meets Non-Functional. NORCAS Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
2018	C	`conf`	Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. VLSI-SoC Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
2017	C	`conf`	A scalable technique to identify true critical paths in sequential circuits. DDECS Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
2017	B	`conf`	Automated area and coverage optimization of minimal latency checkers. ETS Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein
2017	A	`conf`	BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke
2017	C	`conf`	Comprehensive performance and robustness analysis of 2D turn models for network-on-chips. ISCAS Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
2017	—	`conf`	Fault-resilient NoC router with transparent resource allocation. ReCoSoC Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan
2017	C	`conf`	From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein
2017	—	`conf`	High-level test generation for processing elements in many-core systems. ReCoSoC Stephen Adeboye Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
2017	J	`jnl`	Modeling and simulation of circuits with shared structurally synthesized BDDs. Microprocess. Microsystems Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies
2017	Misc	`conf`	Multi-Fragment Markov Model Guided Online Test Generation for MPSoC. ICTERI Jüri Vain, Leonidas Tsiopoulos, Vyacheslav S. Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik
2017	—	`conf`	Resting EEG functional connectivity and graph theoretical measures for discrimination of depression. BHI Laura Orgo, Maie Bachmann, Kaia Kalev, M. Jarvelaid, Jaan Raik, Hiie Hinrikus
2017	—	`ed.`	VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers VLSI-SoC (Selected Papers) Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis
2016	—	`conf`	A novel random approach to diagnostic test generation. NORCAS Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik
2016	A	`conf`	A synthesis-agnostic behavioral fault model for high gate-level fault coverage. DATE Anton Karputkin, Jaan Raik
2016	C	`conf`	Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016	C	`conf`	Foreword. VLSI-SoC Jaan Raik, Ian O'Connor, Thomas Hollstein, Krishnendu Chakrabarty
2016	—	`conf`	Gate-level modelling of NBTI-induced delays under process variations. LATS Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2016	J	`jnl`	Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems. CoRR Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein
2016	J	`jnl`	Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
2016	—	`conf`	Logic-based implementation of fault-tolerant routing in 3D network-on-chips. NOCS Behrad Niazmand, Siavoosh Payandeh Azad, José Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
2016	—	`conf`	Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
2016	—	`conf`	SoCDep ReCoSoC Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein
2015	C	`ed.`	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015 DDECS Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus
2015	—	`conf`	A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. NOCS Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan
2015	C	`conf`	A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. DSD Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein
2015	—	`conf`	Automated minimization of concurrent online checkers for Network-on-Chips. ReCoSoC Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein
2015	—	`conf`	FSMD RTL design manipulation for clock interface abstraction. ICACCI Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
2015	—	`conf`	Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. VLSI-SoC (Selected Papers) Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
2015	J	`jnl`	Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
2015	—	`conf`	Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL. HPCS Jaan Raik
2015	C	`conf`	New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
2015	—	`conf`	Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls
2015	C	`conf`	SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls
2015	C	`conf`	Scalable algorithm for structural fault collapsing in digital circuits. VLSI-SoC Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik
2015	—	`conf`	Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. NORCAS Raimund Ubar, Lembit Jurimagi, Jaan Raik
2015	C	`conf`	SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. DDECS Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
2015	J	`jnl`	Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
2014	—	`conf`	Advanced technical education in the age of cyber physical systems. EWME Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik, Raimund Ubar
2014	J	`jnl`	Automated Design Error Localization in RTL Designs. IEEE Des. Test Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2014	C	`conf`	Critical Path Tracing Based Simulation of Transition Delay Faults. DSD Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
2014	B	`conf`	Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
2014	—	`conf`	Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti
2014	B	`conf`	Logic simulation and fault collapsing with shared structurally synthesized bdds. ETS Dmitri Mironov, Raimund Ubar, Jaan Raik
2013	C	`ed.`	16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013 DDECS Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka
2013	—	`conf`	Assessment of diagnostic test for automated bug localization. LATW Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2013	—	`conf`	At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
2013	J	`jnl`	Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
2013	—	`conf`	Comparison of Model-Based Error Localization algorithms for C designs. EWDTS Urmas Repinski, Jaan Raik
2013	C	`conf`	Extensible open-source framework for translating RTL VHDL IP cores to SystemC. DDECS Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
2013	C	`conf`	Identifying NBTI-Critical Paths in Nanoscale Logic. DSD Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls
2013	—	`conf`	Performance analysis of cosimulating processor core in VHDL and SystemC. ICACCI Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu
2013	—	`conf`	Synthesis of multiple fault oriented test groups from single fault test sets. DTIS Raimund Ubar, Sergei Kostin, Jaan Raik
2012	C	`conf`	A scalable model based RTL framework zamiaCAD for static analysis. VLSI-SoC Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov
2012	—	`conf`	About robustness of test patterns regarding multiple faults. LATW Raimund Ubar, Sergei Kostin, Jaan Raik
2012	—	`conf`	Automated correction of design errors by edge redirection on High-Level Decision Diagrams. ISQED Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2012	B	`conf`	Combining dynamic slicing and mutation operators for ESL correction. ETS Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi
2012	—	`conf`	Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2012	B	`conf`	FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design. ETS Jaan Raik
2012	—	`conf`	FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
2012	C	`conf`	How to Prove that a Circuit is Fault-Free? DSD Raimund Ubar, Sergei Kostin, Jaan Raik
2012	C	`ed.`	IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012 DDECS Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin
2012	J	`jnl`	Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara
2012	—	`conf`	Localization of Bugs in Processor Designs Using zamiaCAD Framework. MTV Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2012	C	`conf`	Low-area boundary BIST architecture for mesh-like network-on-chip. DDECS Jaan Raik, Vineeth Govind
2012	C	`conf`	Multiple stuck-at-fault detection theorem. DDECS Raimund Ubar, Sergei Kostin, Jaan Raik
2012	J	`jnl`	On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2012	—	`conf`	PSL assertion checkers synthesis with ASM based HLS tool ABELITE. LATW Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov
2012	—	`conf`	Ultra-low latency NoC testing via pseudo-random test pattern compaction. ISSoC Hervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide Bertozzi
2011	C	`ed.`	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011 DDECS Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus
2011	—	`conf`	Automated test bench generation for high-level synthesis flow ABELITE. EWDTS Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov
2011	B	`conf`	Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara
2011	C	`conf`	Defect-oriented module-level fault diagnosis in digital circuits. DDECS Sergei Kostin, Raimund Ubar, Jaan Raik
2011	—	`conf`	Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee
2011	—	`conf`	Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. HLDVT Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2011	—	`conf`	Mutation analysis for SystemC designs at TLM. LATW Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2011	C	`conf`	Probabilistic equivalence checking based on high-level decision diagrams. DDECS Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2010	—	`conf`	An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova
2010	C	`conf`	Constraint-based test pattern generation at the Register-Transfer Level. DDECS Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko
2010	J	`jnl`	Evolutionary Approach to Test Generation for Functional BIST CoRR Yuriy A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik
2010	—	`conf`	Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	C	`conf`	Fault collapsing with linear complexity in digital circuits. ISCAS Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2010	—	`conf`	Mutation analysis with high-level decision diagrams. LATW Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi
2010	A	`conf`	Parallel X-fault simulation with critical path tracing technique. DATE Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	—	`conf`	Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2010	C	`conf`	Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2009	C	`conf`	Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. DSD Raimund Ubar, Sergei Kostin, Jaan Raik
2009	J	`jnl`	Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput. Digit. Tech. Jaan Raik, Vineeth Govind, Raimund Ubar
2009	—	`conf`	Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. MSE Raimund Ubar, Artur Jutman, Jaan Raik, Sergei Kostin, Heinz-Dietrich Wuttke
2009	—	`conf`	High-Level Decision Diagrams based coverage metrics for verification and test. LATW Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar
2009	—	`conf`	Investigations of the diagnosibility of digital networks with BIST. LATW Raimund Ubar, Sergei Kostin, Jaan Raik
2009	J	`jnl`	PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electron. Test. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
2009	—	`conf`	Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2008	C	`conf`	Code Coverage Analysis using High-Level Decision Diagrams. DDECS Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee
2008	Misc	`conf`	Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. IDC Eero Ivask, Jaan Raik, Raimund Ubar
2008	J	`jnl`	Embedded fault diagnosis in digital systems with BIST. Microprocess. Microsystems Raimund Ubar, Sergei Kostin, Jaan Raik
2008	C	`conf`	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz
2008	—	`conf`	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee
2008	J	`jnl`	Mixed hierarchical-functional fault models for targeting sequential cores. J. Syst. Archit. Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin
2008	—	`conf`	Parallel fault backtracing for calculation of fault coverage. ASP-DAC Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2008	—	`conf`	Reseeding using compaction of pre-generated LFSR sub-sequences. ICECS Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar
2008	B	`conf`	Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. ETS Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
2008	—	`conf`	Untestable Fault Identification in Sequential Circuits Using Model-Checking. ATS Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko
2008	C	`conf`	Web-Based Framework for Parallel Distributed Test. DDECS Eero Ivask, Jaan Raik, Raimund Ubar
2007	J	`jnl`	FPGA-based fault emulation of synchronous sequential circuits. IET Comput. Digit. Tech. Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar
2007	C	`conf`	Fault Diagnosis in Integrated Circuits with BIST. DSD Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen
2007	C	`conf`	Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus
2007	C	`conf`	Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
2007	B	`conf`	Test Configurations for Diagnosing Faulty Links in NoC Switches. ETS Jaan Raik, Raimund Ubar, Vineeth Govind
2007	B	`conf`	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2006	—	`conf`	An External Test Approach for Network-on-a-Chip Switches. ATS Jaan Raik, Vineeth Govind, Raimund Ubar
2006	—	`conf`	Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar
2006	C	`conf`	High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD Jaan Raik, Raimund Ubar, Taavi Viilukas
2005	J	`jnl`	A New Testability Calculation Method to Guide RTL Test Generation. J. Electron. Test. Jaan Raik, Tanel Nõmmeots, Raimund Ubar
2005	C	`conf`	An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov
2005	B	`conf`	DOT: new deterministic defect-oriented ATPG tool. ETS Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz
2005	C	`conf`	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
2005	Misc	`conf`	Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
2005	C	`conf`	Improved Fault Emulation for Synchronous Sequential Circuits. DSD Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar
2004	B	`conf`	Evaluating Fault Emulation on FPGA. FPL Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe
2004	—	`conf`	Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider
2003	—	`conf`	Multiple-objective backtrace for solving test generation constraints. SoC Andrei Mekler, Jaan Raik
2003	—	`ch.`	Testing Strategies for Networks on Chip. Networks on Chip Raimund Ubar, Jaan Raik
2002	—	`conf`	Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. ICECS Jaan Raik, Artur Jutman, Raimund Ubar
2002	J	`jnl`	Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2002	A	`conf`	Internet-Based Collaborative Test Generation with MOSCITO. DATE André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová
2002	—	`conf`	Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
2001	—	`conf`	Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2001	J	`jnl`	Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectron. Reliab. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2000	C	`conf`	Back-tracing and event-driven techniques in high-level simulation with decision diagrams. ISCAS Raimund Ubar, Jaan Raik, Adam Morawiec
2000	A	`conf`	Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE Adam Morawiec, Raimund Ubar, Jaan Raik
2000	—	`conf`	Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED Raimund Ubar, Jaan Raik
2000	J	`jnl`	Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. Electron. Test. Jaan Raik, Raimund Ubar
2000	—	`conf`	Hierarchical defect-oriented fault simulation for digital circuits. ETW Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
1999	A	`conf`	Cycle-based Simulation with Decision Diagrams. DATE Raimund Ubar, Jaan Raik, Adam Morawiec
1999	—	`conf`	High-level path activation technique to speed up sequential circuit test generation. ETW Jaan Raik, Raimund Ubar
1999	A	`conf`	Sequential Circuit Test Generation Using Decision Diagram Models. DATE Jaan Raik, Raimund Ubar
1997	—	`conf`	Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar