J. V. R. Ravindra

27 papers B 1C 2Misc 1Journal 10Unranked 13

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A Multi-Model Machine Learning Approach for Monitoring Calories Being Burnt During Workouts Using Smart Calorie Tracer. EAI Endorsed Trans. Pervasive Health Technol. Yagnesh Challagundla, Badri Narayanan K, Krishna Sai Devatha, V. C. Bharathi, J. V. R. Ravindra
2024	J	`jnl`	Convolutional Neural Networks in Malaria Diagnosis: A Study on Cell Image Classification. EAI Endorsed Trans. Pervasive Health Technol. Hritwik Ghosh, Irfan Sadiq Rahat, J. V. R. Ravindra, Balajee J, Mohammad Aman Ullah Khan, J. Somasekar
2024	B	`conf`	Deep Learning-Driven Surveillance for Intrusion Identification using Proactive Intelligent Video Recognition. AVSS Yagnesh Challagundla, Shreeya Dheera Parvatham, Sachi Nandan Mohanty, J. V. R. Ravindra
2024	J	`jnl`	Exploring Deep Learning Models for Accurate Alzheimer's Disease Classification based on MRI Imaging. EAI Endorsed Trans. Pervasive Health Technol. Hritwik Ghosh, Pavan Kumar P, Irfan Sadiq Rahat, Md Mehedi Hasan Nipu, Garigipati Rama Krishna, J. V. R. Ravindra
2024	J	`jnl`	Exploring Deep Learning Models for Accurate Alzheimer's Disease Classification based on MRI Imaging. EAI Endorsed Trans. Pervasive Health Technol. Irfan Sadiq Rahat, Tuhin Hossain, Hritwik Ghosh, Kamjula Lakshmi Kanth Reddy, Srinivas Kumar Palvadi, J. V. R. Ravindra
2023	J	`jnl`	Correction to: Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique. Wirel. Pers. Commun. B. Srikanth, J. V. R. Ravindra, P. Ramakrishna, D. Ajitha
2023	J	`jnl`	Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique. Wirel. Pers. Commun. B. Srikanth, J. V. R. Ravindra, P. Ramakrishna, D. Ajitha
2022	J	`jnl`	Proffering Secure Energy Aware Network-On-Chip (Noc) Using Incremental Cryptogine. Sustain. Comput. Informatics Syst. Sangeeta Singh, J. V. R. Ravindra, B. Rajendra Naik
2021	J	`jnl`	Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor. Comput. Electr. Eng. Lavanya Maddisetti, Ranjan K. Senapati, J. V. R. Ravindra
2020	J	`jnl`	The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model. Trans. Emerg. Telecommun. Technol. B. Srikanth, M. Siva Kumar, J. V. R. Ravindra, K. Hari Kishore
2019	—	`conf`	Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters. NORCAS Lavanya Maddisetti, J. V. R. Ravindra
2019	Misc	`conf`	Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers. VLSID Lavanya Maddisetti, J. V. R. Ravindra
2018	—	`conf`	Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters. ICM M. Lavanya, J. V. R. Ravindra
2018	—	`conf`	Performance Metrics of Inexact Multipliers Based on Approximate 5: 2 Compressors. ISOCC Lavanya Maddisetti, J. V. R. Ravindra
2016	—	`conf`	A novel and efficient design of golay encoder for ultra deep submicron technologies. ICACCI Chiranjeevi Sheelam, J. V. R. Ravindra
2016	—	`conf`	Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip. ISOCC Sangeeta Singh, J. V. R. Ravindra, B. Rajendra Naik
2013	—	`conf`	A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications. UKSim J. V. R. Ravindra, Pandurangaiah Yagateela, L. V. Narasimha Prasad
2013	—	`conf`	Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style. EMS Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham
2013	—	`conf`	Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology. EMS Narasimha Rao Konijeti, J. V. R. Ravindra, Pandurangaiah Yagateela
2008	—	`conf`	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI J. V. R. Ravindra, M. B. Srinivas
2007	C	`conf`	A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD J. V. R. Ravindra, M. B. Srinivas
2007	J	`jnl`	Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. J. Circuits Syst. Comput. J. V. R. Ravindra, M. B. Srinivas
2007	—	`conf`	Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net J. V. R. Ravindra, M. B. Srinivas
2007	—	`conf`	Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. SBCCI J. V. R. Ravindra, Srinivas Bala Mandalika
2006	C	`conf`	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
2006	—	`conf`	Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
2005	—	`conf`	A novel deep submicron low power bus coding technique. Circuits, Signals, and Systems K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas