J. S. Yuan

20 papers Misc 1Journal 10Unranked 9
YearRankTypeTitle / Venue / Authors
2014 J jnl
Power amplifier resilient design for process and temperature variations using an on-chip PLL sensing signal.
Microelectron. Reliab.
J. S. Yuan, S. Chen
2013 J jnl
Power amplifier resilient design for process, voltage, and temperature variations.
Microelectron. Reliab.
J. S. Yuan, E. Kritchanchai
2006 J jnl
Dynamic voltage stress effects on nMOS varactor.
Microelectron. Reliab.
Chuanzhao Yu, J. S. Yuan, Enjun Xiao
2005 J jnl
Dynamic stress-induced high-frequency noise degradations in nMOSFETs.
Microelectron. Reliab.
Chuanzhao Yu, J. S. Yuan, Anwar Sadat
2005 J jnl
Hot carrier and soft breakdown effects on LNA performance for ultra wideband communications.
Microelectron. Reliab.
Enjun Xiao, P. P. Ghosh, Chuanzhao Yu, J. S. Yuan
2005 J jnl
Low-power CMOS wireless MEMS motion sensor for physiological activity monitoring.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anwar Sadat, Hongwei Qu, Chuanzhao Yu, J. S. Yuan, Huikai Xie
2005 J jnl
Teaching digital noise and noise margin issues in engineering education.
IEEE Trans. Educ.
J. S. Yuan, Li Yang
2005 J jnl
Voltage stress-induced hot carrier effects on SiGe HBT VCO.
Microelectron. Reliab.
Chuanzhao Yu, Enjun Xiao, J. S. Yuan
2005 J jnl
Voltage stress-induced performance degradation in NMOSFET mixer.
IEICE Electron. Express
Chuanzhao Yu, Hong Yang, Enjun Xiao, J. S. Yuan
2003 — conf
A decoupling technique for CMOS strong-coupled structures.
ACM Great Lakes Symposium on VLSI
Li Yang, J. S. Yuan
2003 Misc conf
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design.
VLSI Design
W. Kuang, J. S. Yuan
2003 — conf
Analyzing Internal-Switching Induced Simultaneous Switching Noise.
ISQED
Li Yang, J. S. Yuan
2003 — conf
Design of enhancement current-balanced logic for mixed-signal ICs.
ISCAS (1)
Li Yang, J. S. Yuan
2003 — conf
Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs.
ISVLSI
Li Yang, J. S. Yuan
2003 — conf
Supply Voltage Scalable System Design Using Self-Timed Circuits.
ISVLSI
W. Kuang, J. S. Yuan, Abdel Ejnioui
2002 — conf
Modeling the output waveform of CMOS gate with feedback effect.
ICECS
Li Yang, J. S. Yuan, M. Hagedorn
2001 — conf
Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology.
ISQED
Wei Li, Qiang Li, J. S. Yuan, Joshua McConkey, Yuan Chen, Sundar Chetlur, Jonathan Zhou, A. S. Oates
1996 — conf
Effects of Ge profiles on base transit time and base resistance of SiGe HBT's.
ICECS
J. Song, J. S. Yuan, F. Schwierz, D. Schipanski
1996 — conf
Scalable bipolar model for BiCMOS and bipolar circuits.
ICECS
Y. Dai, J. S. Yuan, A. M. Phanse, C. S. Yeh, K. Kwang
1988 J jnl
Closed-loop manipulator control using quaternion feedback.
IEEE J. Robotics Autom.
J. S. Yuan