J. Rubén Titos Gil

37 papers A* 3A 5B 5C 4Misc 1Journal 17Unranked 1

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	WoperTM: Got Nacks? Use Them! IEEE Comput. Archit. Lett. Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
2024	A*	`conf`	Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. MICRO Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
2024	J	`jnl`	On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2022	J	`jnl`	Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
2022	C	`conf`	Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2022	J	`jnl`	DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2021	A*	`conf`	Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. MICRO Eduardo José Gómez-Hernández, Juan M. Cebrian, J. Rubén Titos Gil, Stefanos Kaxiras, Alberto Ros
2020	J	`jnl`	Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2020	J	`jnl`	PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2019	J	`jnl`	Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio
2017	A	`conf`	Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2016	J	`jnl`	Architectural support for efficient message passing on shared memory multi-cores. J. Parallel Distributed Comput. J. Rubén Titos Gil, Oscar Palomar, Osman S. Unsal, Adrián Cristal
2016	A	`conf`	Energy minimization at all layers of the data center: The ParaDIME project. DATE Oscar Palomar, Santhosh Kumar Rethinagiri, Gulay Yalcin, J. Rubén Titos Gil, Pablo Prieto, Emma Torrella, Osman S. Unsal, Adrián Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier, Dragomir Milojevic
2015	B	`conf`	DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores. ICPP J. Rubén Titos Gil, Oscar Palomar, Osman S. Unsal, Adrián Cristal
2015	B	`conf`	Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers. ICPP Jochen Hollmann, J. Rubén Titos Gil, Per Stenström
2015	—	`ch.`	Hardware Approaches to Transactional Memory in Chip Multiprocessors. Handbook on Data Centers J. Rubén Titos Gil, Manuel E. Acacio
2015	J	`jnl`	ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers. Microprocess. Microsystems Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Gulay Yalcin, Thomas Knauth, J. Rubén Titos Gil, Pablo Prieto, Malte Schneegaß, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Dragomir Milojevic
2014	A	`conf`	Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. IPDPS Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström
2014	J	`jnl`	Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems. J. Supercomput. Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
2014	J	`jnl`	ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2013	J	`jnl`	Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2013	J	`jnl`	Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2013	J	`jnl`	On the design of energy-efficient hardware transactional memory systems. Concurr. Comput. Pract. Exp. Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
2013	J	`jnl`	SCIN-cache: Fast speculative versioning in multithreaded cores. ACM Trans. Archit. Code Optim. Anurag Negi, J. Rubén Titos Gil
2013	J	`jnl`	Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal
2012	C	`conf`	Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. PDP Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández
2012	J	`jnl`	Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012	A*	`conf`	π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	B	`conf`	Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	B	`conf`	Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2011	—	`conf`	The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	B	`conf`	Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero
2011	A	`conf`	ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2010	C	`conf`	Characterizing Energy Consumption in Hardware Transactional Memory Systems. SBAC-PAD Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
2009	A	`conf`	Speculation-based conflict resolution in hardware transactional memory. IPDPS J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco
2008	C	`conf`	Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco
2008	Misc	`conf`	Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC J. Rubén Titos Gil, Manuel E. Acacio, José M. García