J. Robert Jump

36 papers A* 7B 5Misc 1Journal 20Unranked 3

Year	Rank	Type	Title / Venue / Authors
1994	J	`jnl`	Execution-Driven Simulation of Multiprocessors: Address and Timing Analysis. ACM Trans. Model. Comput. Simul. Sandhya Dwarkadas, J. Robert Jump, James B. Sinclair
1994	—	`conf`	Execution-Driven Simulation of a Superscalar Processor. HICSS (1) H. A. Rizvi, James B. Sinclair, J. Robert Jump, J. Carson
1993	B	`conf`	Execution-Driven Simulation of Shared-Memory Multiprocessors. MASCOTS Sandhya Dwarkadas, J. Robert Jump, R. Mukherjee, James B. Sinclair
1993	B	`conf`	NETSIM: A General-Purpose Interconnection Network Simulator. MASCOTS J. Robert Jump, Sridhar Lakshmanamurthy
1991	J	`jnl`	Efficient Simulation of Parallel Computer Systems. Int. J. Comput. Simul. Richard Covington, Sandhya Dwarkadas, J. Robert Jump, James B. Sinclair, Sridhar Madala
1990	A*	`conf`	Efficient Simulation of Multiprogramming. SIGMETRICS W. P. Dawkins, V. Debbad, J. Robert Jump, James B. Sinclair
1990	J	`jnl`	Evaluation of Reduced Bandwidth Multistage Networks. J. Parallel Distributed Comput. David T. Harper III, J. Robert Jump
1989	B	`conf`	Cross-profiling as an efficient technique in simulating parallel computer systems. COMPSAC Richard Covington, J. Robert Jump, James B. Sinclair
1989	Misc	`conf`	Efficient simulation of cache memories. WSC Sandhya Dwarkadas, J. Robert Jump, James B. Sinclair
1988	A*	`conf`	The Rice Parallel Processing Testbed. SIGMETRICS Richard Covington, Sridhar Madala, V. Mehta, J. Robert Jump, James B. Sinclair
1987	A*	`conf`	Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks. ISCA David T. Harper III, J. Robert Jump
1987	J	`jnl`	Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme. IEEE Trans. Computers David T. Harper III, J. Robert Jump
1986	A*	`conf`	Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme. ISCA David T. Harper III, J. Robert Jump
1986	J	`jnl`	Performance of Unbuffered Shuffle-Exchange Networks. IEEE Trans. Computers Manoj Kumar, J. Robert Jump
1985	A*	`conf`	Matrix Multiplication in an Interleaved Array Processing Architecture. ISCA G. Wolf, J. Robert Jump
1985	J	`jnl`	Switching Strategies in Shuffle-Exchange Packet-Switched Networks. IEEE Trans. Computers Manoj Kumar, Daniel M. Dias, J. Robert Jump
1984	—	`conf`	An interleaved array-processing architecture. AFIPS National Computer Conference J. Robert Jump, James D. Wise, David T. Harper III
1984	J	`jnl`	Performance enhancement in buffered delta networks using crossbar switches and multiple links. J. Parallel Distributed Comput. Manoj Kumar, J. Robert Jump
1983	B	`conf`	Generalized Delta Networks. ICPP Manoj Kumar, J. Robert Jump
1983	A*	`conf`	Switching Strategies in a Class of Packet Switching Networks ISCA Manoj Kumar, Daniel M. Dias, J. Robert Jump
1982	B	`conf`	Augmented and pruned n log n multistaged networks: topology and performance. ICPP Daniel M. Dias, J. Robert Jump
1981	J	`jnl`	Analysis and Simulation of Buffered Delta Networks. IEEE Trans. Computers Daniel M. Dias, J. Robert Jump
1981	J	`jnl`	Packet Switching Interconnection Networks for Modular Systems. Computer Daniel M. Dias, J. Robert Jump
1979	J	`jnl`	On Functional Equivalences in a Model for Parallel Computation Inf. Control. Susan E. Conry, J. Robert Jump
1979	J	`jnl`	Top-Down Design in the Context of Parallel Programs Inf. Control. N. D. Jotwani, J. Robert Jump
1978	J	`jnl`	Effective Pipelining of Digital Systems. IEEE Trans. Computers J. Robert Jump, Sudhir Ahuja
1977	A*	`conf`	A Modular Memory Scheme for Array Processing. ISCA S. R. Ahuja, J. Robert Jump
1975	J	`jnl`	On the Interconnection of Asynchronous Control Structures. J. ACM J. Robert Jump, P. S. Thiagarajan
1974	J	`jnl`	Asynchronous Control Arrays. IEEE Trans. Computers J. Robert Jump
1974	J	`jnl`	On the Interconnection Structure of Cellular Networks Inf. Control. J. Robert Jump, Jayang S. Kirtane
1973	J	`jnl`	On the Equivalence of Asynchronous Control Structures. SIAM J. Comput. J. Robert Jump, P. S. Thiagarajan
1972	J	`jnl`	Microprogrammed Arrays. IEEE Trans. Computers J. Robert Jump, Dennis R. Fritsche
1972	—	`conf`	On the Equivalence of Asynchronous Control Structures SWAT J. Robert Jump, P. S. Thiagarajan
1971	J	`jnl`	On the Length of Feedback Shift Registers Inf. Control. J. Robert Jump, Shreehari Marathe
1970	J	`jnl`	R70-29 Uniform Synthesis of Sequential Circuits. IEEE Trans. Computers J. Robert Jump
1969	J	`jnl`	A Note on the Iterative Decomposition of Finite Automata Inf. Control. J. Robert Jump