J. Robert Heath

23 papers A* 1A 5C 3Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
FPGA-Based Hardware Implementation of Blue-Noise Stacked Error Diffusion Multitoning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Qishi Hu, Daniel L. Lau, Rishvanth Kora Venugopal, J. Robert Heath
2011 — conf
FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm.
SASP
Rishvanth Kora Venugopal, J. Robert Heath, Daniel L. Lau
2010 J jnl
A new multichannel, coherent amplitude modulated, time-division multiplexed, software-defined radio receiver architecture, and field-programmable-gate-array technology implementation.
IEEE Trans. Signal Process.
Veerendra Bhargav Alluri, J. Robert Heath, Michael Lhamon
2009 — conf
A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing.
PDCCS
J. Robert Heath, Nien Y. Lim, Kenneth L. Calvert, Jim Griffioen
2009 — conf
Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform.
PDCCS
J. Robert Heath, Sridhar Hegde, Kanchan Bhide
2008 C conf
A Hand-Held Programmable-Logic-Device Based Temperature and Relative-Humidity Sensor, Processor and Display System Platform for Automation and Control of Industry Processes.
IAS
Phani Tangirala, J. Robert Heath, Arthur Radun, Terry Conners
2007 J jnl
New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets.
J. Electronic Imaging
Albert T. Wong, J. Robert Heath, Michael Lhamon
2004 — conf
ESP: a flexible, high-performance, PLD-based network service.
ICC
M. Muthulakshmi, J. Robert Heath, Kenneth L. Calvert, James Griffioen
2001 C conf
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.
IEEE International Workshop on Rapid System Prototyping
J. Robert Heath, Andrew Tan
2000 J jnl
High speed storage area networks using a fibre channel arbitrated loop interconnect.
IEEE Netw.
J. Robert Heath, Peter Yakutis
1997 J jnl
Development, Analysis, and Verification of a Parallel Hybrid Dataflow Computer Architectural Framework and Associated Load-Balancing Strategies and Algorithms via Parallel Simulation.
Simul.
J. Robert Heath, Balasubramanian Sivanesa
1994 J jnl
PARALLEX: a parallel approach to switchbox routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tae Won Cho, Sam S. Pyo, J. Robert Heath
1992 — conf
A new conflict resolving switchbox router.
Great Lakes Symposium on VLSI
Tae Won Cho, Sam S. Pyo, J. Robert Heath
1988 C conf
A methodology for the control and custom VLSI implementation of large-scale Clos networks.
ICCD
J. Robert Heath, Eric Allen Disch
1986 J jnl
A note on "Realization of digital filters using input-scaled floating-point arithmetic".
IEEE Trans. Acoust. Speech Signal Process.
J. Robert Heath
1984 A conf
An Integrated-Circuit Crossbar Switching System Design.
ICDCS
George Broomell, J. Robert Heath
1983 J jnl
Classification Categories and Historical Development of Circuit Switching Topologies.
ACM Comput. Surv.
George Broomell, J. Robert Heath
1982 A conf
A Hardware Task Scheduling Mechanism for a Real-Time Multi-Microprocessor Architecture.
RTSS
Andrew D. Hurt, J. Robert Heath
1982 A conf
A distributed computer architecture for real-time, data driven applications.
ICDCS
J. Robert Heath, George Broomell, Andrew D. Hurt
1982 A conf
The Design of a Fault-Tolerant Computing Element for Distributed Data Processors.
ICDCS
Andrew D. Hurt, J. Robert Heath
1981 J jnl
How to Write a Universal Cross-Assembler.
IEEE Micro
J. Robert Heath, Shailesh Patel
1980 A conf
The Complexity and Use of a Multistage Interconnection Network for Distributed Processing Systems.
RTSS
J. Robert Heath, James Cline
1977 A* conf
CDL - A tool for concurrent hardware and software development.
DAC
J. Robert Heath, Bill D. Carroll, Terry T. Cwik