Ivan S. Kourtev

25 papers A 1Misc 1Journal 6Unranked 16

Year	Rank	Type	Title / Venue / Authors
2009	J	`jnl`	Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits. J. Circuits Syst. Comput. Baris Taskin, Ivan S. Kourtev
2006	J	`jnl`	Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Baris Taskin, Ivan S. Kourtev
2006	Misc	`conf`	Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
2006	J	`jnl`	Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocess. Microsystems Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
2005	—	`conf`	Delay insertion method in clock skew scheduling. ISPD Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	A 64-way VLIW/SIMD FPGA architecture and design flow. ICECS Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh
2004	—	`conf`	Advanced timing of level-sensitive sequential circuits. ICECS Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	Efficient CAD development for emerging technologies using Objective-C and Cocoa. ICECS Bryan A. Brady, Alex K. Jones, Ivan S. Kourtev
2004	—	`conf`	LURU: global-scope FPGA technology mapping with content-addressable memories. ICECS Joshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
2004	J	`jnl`	Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	Performance improvement of edge-triggered sequential circuits. ICECS Baris Taskin, Ivan S. Kourtev
2004	—	`conf`	Performance metrics for asynchronous digital circuits applicable to computer-aided design. ISCAS (5) Rajani Parthasarthy, Ivan S. Kourtev
2004	J	`jnl`	Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. Very Large Scale Integr. Syst. Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman
2004	—	`conf`	Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) Baris Taskin, Ivan S. Kourtev
2003	—	`conf`	Reduced dynamic swing domino logic. ACM Great Lakes Symposium on VLSI Roy Mader, Ivan S. Kourtev
2003	—	`conf`	Short Courses in System-on-a-Chip (SoC) Design. MSE Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis
2003	—	`conf`	The Sandbox Design Experience Course. MSE Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis
2002	J	`jnl`	Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. J. Circuits Syst. Comput. Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman
2002	—	`conf`	Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev
2002	—	`conf`	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems Baris Taskin, Ivan S. Kourtev
2001	—	`conf`	A single latch, high speed double-edge triggered flip-flop (DETFF). ICECS Troy A. Johnson, Ivan S. Kourtev
2001	—	`conf`	Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. ICECS Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman
1999	A	`conf`	Clock skew scheduling for improved reliability via quadratic programming. ICCAD Ivan S. Kourtev, Eby G. Friedman
1999	—	`conf`	Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
1999	—	`ch.`	System Timing. The VLSI Handbook Ivan S. Kourtev, Eby G. Friedman