Ivan Miro Panades

31 papers A* 1A 2B 1C 5Journal 7Unranked 15

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. VLSI Circuits Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Anthony Quelen, Emmanuel Pluchart, Jean-Philippe Noel, Reda Boumchedda, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Alexandre Valentian, Frédéric Heitzmann, Edith Beigné, Fabien Clermidy
2018	—	`conf`	A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet
2018	—	`conf`	Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. ICECS Mickael Maman, Dominique Morche, Baudouin Martineau, Clement Jany, Ivan Miro Panades, Anthony Quelen, Franck Badets, Edith Beigné
2018	—	`conf`	LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition. ESSCIRC Anthony Quelen, Guilherme Migliato Marega, Sylvain Bouquet, Ivan Miro Panades, Gaël Pillonnet
2017	J	`jnl`	A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi
2017	J	`jnl`	A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel
2017	J	`jnl`	Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017	C	`conf`	In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart
2016	—	`conf`	193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016	—	`conf`	8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos
2015	—	`conf`	3D advanced integration technology for heterogeneous systems. 3DIC Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy
2015	J	`jnl`	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015	—	`conf`	An optical clock receiver based on an injection locked ring oscillator featuring auto-calibration. MWSCAS Robert Polster, Jose-Luis Gonzalez Jimenez, Ivan Miro Panades, Eric Cassan
2015	C	`conf`	Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet
2015	—	`conf`	Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. ISVLSI Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy
2014	—	`conf`	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2014	J	`jnl`	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
2014	C	`conf`	Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. IOLTS Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman
2014	A*	`conf`	Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres
2014	B	`conf`	Shadow-scan design with low latency overhead and in-situ slack-time monitoring. ETS Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman
2013	A	`conf`	3D integration for power-efficient computing. DATE Denis Dutoit, Eric Guthmuller, Ivan Miro Panades
2013	C	`conf`	3D stacking for multi-core architectures: From WIDEIO to distributed caches. ISCAS Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Pascal Vivet
2013	C	`conf`	Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. VLSI-SoC Eric Guthmuller, Ivan Miro Panades, Alain Greiner
2012	—	`conf`	Adaptive Stackable 3D Cache Architecture for Manycores. ISVLSI Eric Guthmuller, Ivan Miro Panades, Alain Greiner
2011	J	`jnl`	Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq
2010	—	`conf`	A 477mW NoC-based digital baseband for MIMO 4G SDR. ISSCC Fabien Clermidy, Christian Bernard, Romain Lemaire, Jérôme Martin, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet, Norbert Wehn
2008	J	`jnl`	Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Des. Test Comput. Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades
2008	—	`conf`	Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NOCS Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner
2007	—	`conf`	Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. NOCS Ivan Miro Panades, Alain Greiner
2007	A	`conf`	Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. DATE Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner
2006	—	`conf`	A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. Nano-Net Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad