Ivan de Paúl

17 papers B 2C 3Misc 1Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
Design Guidelines for β-Multiplier Current Reference Circuits.
DCIS
Sebastià A. Bota, Rafel Perelló, Salvador Barceló, Ivan de Paúl, Jaume Segura, Jaume Verd
2024 J jnl
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results.
CoRR
Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura
2023 — conf
A Compact Double-Exponential Circuit for Single Event Transient Emulation.
DCIS
Sebastià A. Bota, Salvador Barceló, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura
2022 — conf
Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring.
IEEE SENSORS
Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura
2018 C conf
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator.
ISCAS
Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd
2013 C conf
Accurate alpha soft error rate evaluation in SRAM memories.
IOLTS
Sebastià A. Bota, Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, L. A. Segura
2009 — conf
Practical Hardware Implementation of Self-configuring Neural Networks.
ISNN (3)
José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl
2009 — conf
Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis.
ICANN (1)
José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro
2008 J jnl
A simple CMOS chaotic integrated circuit.
IEICE Electron. Express
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Sebastià A. Bota, Antoni Morro
2008 J jnl
Self-configuring spiking neural networks.
IEICE Electron. Express
José Luis Rosselló, Ivan de Paúl, Vincent Canals
2008 B conf
Using stochastic logic for efficient pattern recognition analysis.
IJCNN
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura
2007 J jnl
Charge-based testing BIST for embedded memories.
IET Comput. Digit. Tech.
Bartomeu Alorda, Ivan de Paúl, Jaume Segura
2006 B conf
A Fully CMOS Low-Cost Chaotic Neural Network.
IJCNN
José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
2004 C conf
A BIST-based Charge Analysis for Embedded Memories.
IOLTS
Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura
2002 — conf
SEU fault injection in simulation environments: example of VHDL configuration on FPGA device.
LATW
Ivan de Paúl, Miquel Roca, Oscar Calvo, Raul Velazco
2001 Misc conf
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments.
VTS
Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden
2000 — conf
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor.
IOLTW
Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller