Iuliana P. Radu

31 papers A 2Journal 2Unranked 27

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure. VLSI Technology and Circuits Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Shreyam Natani, San Lin Liew, Carlo Gilardi, Hsin-Yuan Chiu, Sheng-Kai Su, Andrew Bechdolt, Gilad Zeevi, Zichen Zhang, Matthias Passlack, Vincent D.-H. Hou, Harshil Kashyap, Chao-Hsin Chien, Prabhakar Bandaru, Andrew C. Kummel, H.-S. Philip Wong, Subhasish Mitra, Gregory Pitner, Iuliana P. Radu
2024	—	`conf`	On the Extreme Scaling of Transistors with Monolayer MOS2 Channel. VLSI Technology and Circuits Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Edward Chen, Chen-Feng Hsu, Walker Yun, Hsiang-Chi Hu, Bo-Heng Liu, T. Y. Lee, Chi-Chung Kei, Wen-Hao Chang, Jin Cai, W. Jeff, Chung-Cheng Wu, H.-S. Philip Wong, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu
2023	—	`conf`	Building high performance transistors on carbon nanotube channel. VLSI Technology and Circuits Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu
2023	—	`conf`	Comprehensive 300 mm process for Silicon spin qubits with modular integration. VLSI Technology and Circuits A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, Ruoyu Li, Iuliana P. Radu, Pol Van Dorpe, Kristiaan De Greve
2023	—	`conf`	How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. VLSI Technology and Circuits H.-L. Chiang, Richard A. Hadi, J.-F. Wang, Hung-Chi Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, Christian C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu
2023	—	`conf`	MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. ESSDERC W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu
2023	—	`conf`	Scaled contact length with low contact resistance in monolayer 2D channel transistors. VLSI Technology and Circuits Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu
2022	—	`conf`	Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi
2022	—	`conf`	Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS. VLSI Technology and Circuits Sheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu
2022	—	`conf`	Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu
2022	—	`conf`	Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor. VLSI Technology and Circuits Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana P. Radu, H.-S. Philip Wong, Han Wang
2021	—	`conf`	Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSCIRC Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor
2021	—	`conf`	Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSDERC Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor
2021	A	`conf`	Circuit models for the co-simulation of superconducting quantum computing systems. DATE Rohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor
2021	—	`conf`	On MX2-based metal-oxide-semiconductor device capacitance-voltage characteristics and dual-gate operation. DRC Dennis Lin, Xiangyu Wu, Vivek Mootheri, Daire Cott, Benjamin Groven, Pierre Morin, Inge Asselberghs, Iuliana P. Radu
2021	—	`conf`	Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing. VLSI Circuits Iuliana P. Radu, Roy Li, Anton Potocnik, Tsvetan Ivanov, Danny Wan, Stefan Kubicek, Nard I. Dumoulin Stuyck, Jeroen Verjauw, Julien Jussot, Yann Canvel, Clement Godfrin, Massimo Mongillo, Rohith Acharya, Asser Elsayed, Mohamed Shehata, Xiaoyu Piao, Antoine Pacco, Laurent Souriau, Sebastien Couet, B. T. Chan, Jan Craninckx, Bertrand Parvais, Alexander Grill, Subramanian Narasimhamoorthy, Steven Van Winckel, Steven Brebels, Fahd A. Mohiyaddin, George Simion, Bogdan Govoreanu
2021	—	`conf`	Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process. VLSI Circuits Nard I. Dumoulin Stuyck, Roy Li, Clement Godfrin, Asser Elsayed, Stefan Kubicek, Julien Jussot, B. T. Chan, Fahd A. Mohiyaddin, Mohamed Shehata, George Simion, Yann Canvel, Ludovic Goux, Heyns Heyns, Bogdan Govoreanu, Iuliana P. Radu
2020	—	`conf`	Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures. IRPS Jakob Michl, Alexander Grill, Dieter Claes, Gerhard Rzepa, Ben Kaczer, Dimitri Linten, Iuliana P. Radu, Tibor Grasser, Michael Waltl
2020	—	`conf`	Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures. IRPS Alexander Grill, Erik Bury, Jakob Michl, Stanislav Tyaginov, Dimitri Linten, Tibor Grasser, Bertrand Parvais, Ben Kaczer, Michael Waltl, Iuliana P. Radu
2019	J	`jnl`	Reconfigurable nanoscale spin wave majority gate with frequency-division multiplexing. CoRR Giacomo Talmelli, Thibaut Devolder, Nick Träger, Johannes Förster, Sebastian Wintz, Markus Weigand, Hermann Stoll, Marc M. Heyns, Gisela Schütz, Iuliana P. Radu, Joachim Gräfe, Florin Ciubotaru, Christoph Adelmann
2019	—	`conf`	Tunnel FETs using Phosphorene/ReS2 heterostructures. DRC Yashwanth Balaji, Quentin Smets, Dennis Lin, Inge Asselberghs, Iuliana P. Radu, Guido Groeseneken
2018	—	`conf`	Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. DRC Giovanni V. Resta, Yashwanth Balaji, Dennis Lin, Iuliana P. Radu, Francky Catthoor, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2018	—	`conf`	Spin-based majority gates for logic applications. DRC Iuliana P. Radu
2018	A	`conf`	Towards high-performance polarity-controllable FETs with 2D materials. DATE Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Material selection and device design guidelines for two-dimensional materials based TFETs. ESSDERC Tarun Agarwal, Bart Soree, Iuliana P. Radu, Praveen Raghavan, Gianluca Fiori, Marc M. Heyns, Wim Dehaene
2017	—	`conf`	Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures. ESSDERC Yashwanth Balaji, Quentin Smets, Cesar J. Lockhart de la Rosa, Anh Khoa Augustin Lu, Daniele Chiappe, Tarun Agarwal, Dennis Lin, Cedric Huyghebaert, Iuliana P. Radu, Dan Mocuta, Guido Groeseneken
2017	—	`conf`	WS2 transistors on 300 mm wafers with BEOL compatibility. ESSDERC Tom Schram, Quentin Smets, Benjamin Groven, M. H. Heyne, E. Kunnen, A. Thiam, Katia Devriendt, Annelies Delabie, Dennis Lin, M. Lux, Daniele Chiappe, Inge Asselberghs, S. Brus, Cedric Huyghebaert, S. Sayan, A. Juncker, Matty Caymax, Iuliana P. Radu
2016	—	`conf`	Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. ESSCIRC Tarun Agarwal, Iuliana P. Radu, Praveen Raghavan, Gianluca Fiori, Aaron Thean, Marc M. Heyns, Wim Dehaene
2016	J	`jnl`	Non-volatile spin wave majority gate at the nanoscale. CoRR Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu
2015	—	`conf`	Area and routing efficiency of SWD circuits compared to advanced CMOS. ICICDT Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean
2014	—	`conf`	System-level assessment and area evaluation of Spin Wave logic circuits. NANOARCH Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean