Iuliana Bacivarov

43 papers A* 2A 5C 2Misc 5Journal 10Unranked 16

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. Pier Stanislao Paolucci, Andrea Biagioni, Luis Gabriel Murillo, Frédéric Rousseau, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Devendra Rai, Davide Rossetti, Francesco Simula
2014	Misc	`conf`	AdaPNet: Adapting process networks in response to resource variations. CASES Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele
2014	A	`conf`	COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors. DATE Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2014	J	`jnl`	EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes. CoRR Pier Stanislao Paolucci, Iuliana Bacivarov, Devendra Rai, Lars Schor, Lothar Thiele, Hoeseok Yang, Elena Pastorelli, Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Francesco Simula, Laura Tosoratto, Piero Vicini
2014	C	`conf`	EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. ISPA Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frédéric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock
2014	A	`conf`	Reliability-aware mapping optimization of multi-core systems with mixed-criticality. DATE Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele
2014	A*	`conf`	Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs. DAC Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele
2013	—	`conf`	Designing Applications with Predictable Runtime Characteristics for the Baremetal Intel SCC. Euro-Par Workshops Devendra Rai, Lars Schor, Nikolay Stoimenov, Iuliana Bacivarov, Lothar Thiele
2013	J	`jnl`	EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment CoRR Pier Stanislao Paolucci, Iuliana Bacivarov, Gert Goossens, Rainer Leupers, Frédéric Rousseau, Christoph Schumacher, Lothar Thiele, Piero Vicini
2013	J	`jnl`	Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs. J. Electron. Test. Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele
2013	Misc	`conf`	Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism. CASES Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2013	—	`ch.`	Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip. Handbook of Signal Processing Systems Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele
2013	J	`jnl`	Predictability for timing and temperature in multiprocessor system-on-chip platforms. ACM Trans. Embed. Comput. Syst. Lothar Thiele, Lars Schor, Iuliana Bacivarov, Hoeseok Yang
2013	J	`jnl`	Real-time worst-case temperature analysis with temperature-dependent parameters. Real Time Syst. Hoeseok Yang, Iuliana Bacivarov, Devendra Rai, Jian-Jia Chen, Lothar Thiele
2013	—	`conf`	Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor. Euro-Par Workshops Lars Schor, Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2012	J	`jnl`	Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications. ACM Trans. Embed. Comput. Syst. Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Matthias Keller, Lothar Thiele
2012	—	`conf`	Fast worst-case peak temperature evaluation for real-time applications on multi-core systems. LATW Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele
2012	C	`conf`	MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC. DSD Olivera Jovanovic, Peter Marwedel, Iuliana Bacivarov, Lothar Thiele
2012	—	`conf`	Multi-objective mapping optimization via problem decomposition for many-core systems. ESTIMedia Shin-Haeng Kang, Hoeseok Yang, Lars Schor, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele
2012	—	`conf`	PRO3D: programming for future 3D manycore architectures. INA-OCMC@HiPEAC Christian Fabre, Iuliana Bacivarov, Eth Zürich, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand
2012	Misc	`conf`	Power agnostic technique for efficient temperature estimation of multicore embedded systems. CASES Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2012	Misc	`conf`	Scenario-based design flow for mapping streaming applications onto on-chip many-core systems. CASES Lars Schor, Iuliana Bacivarov, Devendra Rai, Hoeseok Yang, Shin-Haeng Kang, Lothar Thiele
2012	A	`conf`	Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems. IEEE Real-Time and Embedded Technology and Applications Symposium Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele
2012	J	`jnl`	Worst-case temperature analysis for different resource models. IET Circuits Devices Syst. Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2011	Misc	`conf`	Mapping of applications to MPSoCs. CODES+ISSS Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang
2011	—	`conf`	PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status. FMCO Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, Diego Melpignano
2011	—	`conf`	Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems. FMCO Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2011	A*	`conf`	Thermal-aware system analysis and software synthesis for embedded multi-processors. DAC Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov
2011	—	`conf`	Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. PATMOS Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
2011	A	`conf`	Worst-case temperature analysis for real-time systems. DATE Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele
2010	—	`ch.`	Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip. Handbook of Signal Processing Systems Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele
2009	—	`conf`	A modular fast simulation framework for stream-oriented MPSoC. SIES Kai Huang, Iuliana Bacivarov, Jun Liu, Wolfgang Haid
2009	—	`conf`	Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs. ESTIMedia Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Bacivarov, Lothar Thiele
2009	—	`conf`	Generation and calibration of compositional performance analysis models for multi-processor systems. ICSAMOS Wolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, Lothar Thiele
2009	J	`jnl`	Multiprocessor SoC software design flows. IEEE Signal Process. Mag. Wolfgang Haid, Kai Huang, Iuliana Bacivarov, Lothar Thiele
2008	—	`conf`	Scalably distributed SystemC simulation for embedded applications. SIES Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, Lothar Thiele
2007	—	`conf`	Mapping Applications to Tiled Multiprocessor Embedded Systems. ACSD Lothar Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang
2006	—	`conf`	Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE Designers' Forum Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya
2005	J	`jnl`	ChronoSym: a new approach for fast and accurate SoC cosimulation. Int. J. Embed. Syst. Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya
2005	—	`conf`	Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. ASP-DAC Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya
2003	A	`conf`	Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. DATE Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya
2003	—	`ch.`	Multi-Level Software Validation for NoC. Networks on Chip Sungjoo Yoo, Gabriela Nicolescu, Iuliana Bacivarov, Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya
2002	—	`conf`	Timed HW-SW cosimulation using native execution of OS and application SW. HLDVT Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya