Ishwar Parulkar

20 papers A* 4A 8B 1C 1Journal 5Unranked 1

Year	Rank	Type	Title / Venue / Authors
2010	A	`conf`	Panel: Reliability of data centers: Hardware vs. software. DATE Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota
2009	J	`jnl`	Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. IEEE J. Solid State Circuits Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar
2009	J	`jnl`	Comprehensive Approach to High-Performance Server Chipset Debug. IEEE Des. Test Comput. Ishwar Parulkar, Babu Turumella
2009	B	`conf`	Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. ETS Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar
2008	A	`conf`	DFX of a 3 ITC Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar
2008	—	`conf`	Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor. ISSCC Georgios K. Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar
2008	A	`conf`	Silent Data Corruption - Myth or reality? DSN Cristian Constantinescu, Ishwar Parulkar, R. Harper, Sarah Michalak
2005	A	`conf`	Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. ITC Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski
2005	A	`conf`	Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field. ITC Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar
2005	C	`conf`	Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. IOLTS Ishwar Parulkar, Robert Cypher
2003	A	`conf`	Latch Divergency In Microprocessor Failure Analysis. ITC Peter Dahlgren, Paul Dickinson, Ishwar Parulkar
2002	A	`conf`	A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC ITC Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar
2001	J	`jnl`	Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	J	`jnl`	Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	J	`jnl`	Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	A*	`conf`	Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998	A	`conf`	Scheduling and Module Assignment for Reducing Bist Resources. DATE Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1996	A*	`conf`	Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1995	A*	`conf`	Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1994	A*	`conf`	Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC Ishwar Parulkar, Melvin A. Breuer, Charles Njinda