Ishan G. Thakkar

83 papers A* 2A 2C 4Misc 7Journal 41Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ASTRA: A Stochastic Transformer Neural Network Accelerator with Silicon Photonics. ACM Trans. Embed. Comput. Syst. Salma Afifi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar, Sudeep Pasricha
2025	—	`conf`	A Light-Speed Large Language Model Accelerator with Optical Stochastic Computing. ACM Great Lakes Symposium on VLSI Salma Afifi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar, Sudeep Pasricha
2025	J	`jnl`	STAR: A Mixed Analog Stochastic In-DRAM Convolutional Neural Network Accelerator. IEEE Des. Test Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha
2025	A	`conf`	SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators. DATE Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha
2025	C	`conf`	Scaling Up the Sustainability of Photonic Tensor Cores With Device-Circuit-Signaling Co-Design. ICCD Ishan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo
2024	—	`conf`	A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators. ISQED Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar
2024	J	`jnl`	A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators. CoRR Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar
2024	—	`conf`	A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics. ISQED Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Oluwaseun Adewunmi Alo, Jeffrey Todd Hastings, Justin Scott Woods
2024	J	`jnl`	A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics. CoRR Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Oluwaseun Adewunmi Alo, Jeffrey Todd Hastings, Justin Scott Woods
2024	J	`jnl`	ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks. CoRR Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha
2024	J	`jnl`	ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha
2024	J	`jnl`	An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects. ACM J. Emerg. Technol. Comput. Syst. Venkata Sai Praneeth Karempudi, Janibul Bashir, Ishan G. Thakkar
2024	J	`jnl`	HEANA: A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference. CoRR Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar
2024	—	`ch.`	Low-Latency, Energy-Efficient In-DRAM CNN Acceleration with Bit-Parallel Unary Computing. Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Hardware Architectures Ishan G. Thakkar, Supreeth Mysore Shivanandamurthy, Sayed Ahmad Salehi
2024	—	`conf`	Mixed Delay/Nondelay Embeddings Based Neuromorphic Computing with Patterned Nanomagnet Arrays. ICRC Changpeng Ti, Usman Hassan, Sairam Sri Vatsavai, Margaret McCarter, Aastha Vasdev, Jincheng An, Barat Achinuq, Ulrich Welp, Sen-Ching S. Cheung, Ishan G. Thakkar, Jeffrey Todd Hastings
2024	J	`jnl`	Mixed Delay/Nondelay Embeddings Based Neuromorphic Computing with Patterned Nanomagnet Arrays. CoRR Changpeng Ti, Usman Hassan, Sairam Sri Vatsavai, Margaret McCarter, Aastha Vasdev, Jincheng An, Barat Achinuq, Ulrich Welp, Sen-Ching S. Cheung, Ishan G. Thakkar, Jeffrey Todd Hastings
2024	—	`ch.`	Photonic NoCs for Energy-Efficient Data-Centric Computing. Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Hardware Architectures Febin P. Sunny, Asif Mirza, Ishan G. Thakkar, Mahdi Nikdast, Sudeep Pasricha
2024	J	`jnl`	SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators. CoRR Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha
2024	—	`conf`	Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels. ISVLSI Oluwaseun Adewunmi Alo, Sairam Sri Vatsavai, Ishan G. Thakkar
2024	J	`jnl`	Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels. CoRR Oluwaseun Adewunmi Alo, Sairam Sri Vatsavai, Ishan G. Thakkar
2023	—	`conf`	A Bit-Parallel Deterministic Stochastic Multiplier. ISQED Sairam Sri Vatsavai, Ishan G. Thakkar
2023	J	`jnl`	A Bit-Parallel Deterministic Stochastic Multiplier. CoRR Sairam Sri Vatsavai, Ishan G. Thakkar
2023	—	`conf`	A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits. ISQED Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Jeffrey Todd Hastings
2023	J	`jnl`	A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits. CoRR Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Jeffrey Todd Hastings
2023	J	`jnl`	A Silicon Nitride Microring Modulator for High-Performance Photonic Integrated Circuits. CoRR Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Jeffrey Todd Hastings
2023	—	`conf`	AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning. ISQED Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi
2023	J	`jnl`	AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning. CoRR Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi
2023	J	`jnl`	An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects. CoRR Venkata Sai Praneeth Karempudi, Janibul Bashir, Ishan G. Thakkar
2023	—	`conf`	An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks. ISQED Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar
2023	J	`jnl`	An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks. CoRR Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar
2023	—	`conf`	High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures. ACM Great Lakes Symposium on VLSI Ishan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi
2023	J	`jnl`	High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures. CoRR Ishan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi
2023	A	`conf`	SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs. IPDPS Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Sayed Ahmad Salehi, Jeffrey Todd Hastings
2023	J	`jnl`	SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs. CoRR Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Sayed Ahmad Salehi, Jeffrey Todd Hastings
2022	—	`conf`	A Silicon Nitride Microring Based High-Speed, Tuning-Efficient, Electro-Refractive Modulator. iSES Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Jeffrey Todd Hastings
2022	J	`jnl`	Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro Amlan Ganguly, Sergi Abadal, Ishan G. Thakkar, Natalie Enright Jerger, Marc D. Riedel, Masoud Babaie, Rajeev Balasubramonian, Abu Sebastian, Sudeep Pasricha, Baris Taskin
2022	J	`jnl`	Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study. ACM J. Emerg. Technol. Comput. Syst. Venkata Sai Praneeth Karempudi, Febin Sunny, Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Mahdi Nikdast, Sudeep Pasricha
2022	J	`jnl`	Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sairam Sri Vatsavai, Ishan G. Thakkar
2022	J	`jnl`	Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-Sized Tensors. CoRR Sairam Sri Vatsavai, Ishan G. Thakkar
2021	J	`jnl`	ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Febin P. Sunny, Asif Mirza, Ishan G. Thakkar, Mahdi Nikdast, Sudeep Pasricha
2021	J	`jnl`	ARXON: A Framework for Approximate Communication over Photonic Networks-on-Chip. CoRR Febin Sunny, Asif Mirza, Ishan G. Thakkar, Mahdi Nikdast, Sudeep Pasricha
2021	—	`conf`	ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing. ISVLSI Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi
2021	J	`jnl`	ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing. CoRR Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi
2021	—	`conf`	Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. ACM Great Lakes Symposium on VLSI Bobby Bose, Ishan G. Thakkar
2021	J	`jnl`	Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. CoRR Bobby Bose, Ishan G. Thakkar
2021	Misc	`conf`	Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit. SenSys Venkata Sai Praneeth Karempudi, Shreyan Datta, Ishan G. Thakkar
2021	J	`jnl`	Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha, Sairam Sri Vatsavai, Varun Bhat
2021	J	`jnl`	ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM. CoRR Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi
2021	J	`jnl`	Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study. CoRR Venkata Sai Praneeth Karempudi, Febin Sunny, Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Mahdi Nikdast, Sudeep Pasricha
2021	Misc	`conf`	Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. VLSID Sairam Sri Vatsavai, Ishan G. Thakkar
2021	J	`jnl`	Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. CoRR Sairam Sri Vatsavai, Ishan G. Thakkar
2020	J	`jnl`	Exploiting Process Variations to Secure Photonic NoC Architectures from Snooping Attacks. CoRR Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha, Sairam Sri Vatsavai, Varun Bhat
2020	C	`conf`	Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. ICCD Chao-Hsuan Huang, Ishan G. Thakkar
2020	—	`conf`	LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip. ACM Great Lakes Symposium on VLSI Febin Sunny, Asif Mirza, Ishan G. Thakkar, Sudeep Pasricha, Mahdi Nikdast
2020	J	`jnl`	LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip. CoRR Febin Sunny, Asif Mirza, Ishan G. Thakkar, Sudeep Pasricha, Mahdi Nikdast
2020	J	`jnl`	Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. CoRR Chao-Hsuan Huang, Ishan G. Thakkar
2020	—	`conf`	PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance. NOCS Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar
2020	J	`jnl`	PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance. CoRR Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar
2020	—	`conf`	Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication. ACM Great Lakes Symposium on VLSI Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar
2020	J	`jnl`	Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication. CoRR Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar
2019	Misc	`conf`	A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress. CODES+ISSS Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi
2019	—	`conf`	Mitigating Write Disturbance in Phase Change Memory Architectures. CASES (work in progress) Chao-Hsuan Huang, Ishan G. Thakkar
2019	Misc	`conf`	Mitigating inter-channel crosstalk non-uniformity in microring filter arrays of photonic NoCs: work-in-progress. CODES+ISSS Venkata Sai Praneeth Karempudi, Ishan G. Thakkar
2018	—	`conf`	Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip. ACM Great Lakes Symposium on VLSI Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar
2018	J	`jnl`	DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ishan G. Thakkar, Sudeep Pasricha
2018	J	`jnl`	HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs. IEEE Trans. Very Large Scale Integr. Syst. Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha
2018	J	`jnl`	LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip. IEEE Trans. Multi Scale Comput. Syst. Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha
2018	—	`conf`	Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling. IGSC Ishan G. Thakkar, Sudeep Pasricha
2018	A*	`conf`	SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. DAC Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha
2018	—	`conf`	Securing Photonic NoC Architectures from Hardware Trojans. NOCS Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat
2017	—	`conf`	Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. SLIP Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha
2017	Misc	`conf`	DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. VLSID Ishan G. Thakkar, Sudeep Pasricha
2017	—	`conf`	Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling. NOCS Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha
2016	—	`conf`	A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects. SLIP Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha
2016	Misc	`conf`	Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures. VLSID Ishan G. Thakkar, Sudeep Pasricha
2016	Misc	`conf`	Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling. CODES+ISSS Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha
2016	A*	`conf`	PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs. DAC Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha
2016	—	`conf`	Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures. ISQED Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha
2016	—	`conf`	Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers. NOCS Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha
2015	J	`jnl`	3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization. IEEE Des. Test Ishan G. Thakkar, Sudeep Pasricha
2015	J	`jnl`	3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead. IEEE Trans. Multi Scale Comput. Syst. Ishan G. Thakkar, Sudeep Pasricha
2015	C	`conf`	A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses. ICCD Ishan G. Thakkar, Sudeep Pasricha
2014	C	`conf`	3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time. ICCD Ishan G. Thakkar, Sudeep Pasricha