Irith Pomeranz

772 papers A* 29A 102B 17C 29Misc 98Journal 352Unranked 145
YearRankTypeTitle / Venue / Authors
2026 J jnl
Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2026 J jnl
Aging Aware Test Generation Procedure for Multicycle Scan-Based Tests.
IEEE Access
Irith Pomeranz
2026 J jnl
Minimal Set of Primary Input Vector Pairs for Two-Cycle Gate-Exhaustive Faults.
IEEE Access
Irith Pomeranz
2026 J jnl
Modular Functional Test Sequences for Test Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2026 J jnl
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2026 J jnl
Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2026 J jnl
Reverse Steepening of a Fault Coverage Curve.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2026 J jnl
Test Generation for Subcircuits With High-Functional Switching Activities.
IEEE Access
Irith Pomeranz
2025 J jnl
Arranging a Pool of Functional Test Sequences for Variable In-Field Test Periods.
IEEE Access
Irith Pomeranz
2025 J jnl
COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2025 Misc conf
Chip Aging and Double Transition Faults.
VTS
Irith Pomeranz
2025 J jnl
Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2025 J jnl
Close-to-Functional Simulation-Model-Based Tests for Single-Cycle Interconnect Faults.
IEEE Access
Irith Pomeranz
2025 J jnl
DTGx2: Dual Target Diagnostic Test Generation.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2025 J jnl
DYCOCO: Dynamic Configuration-Based Test Compaction.
IEEE Access
Irith Pomeranz
2025 J jnl
Diagnostic Test Compaction of Functional Test Sequences.
IEEE Access
Irith Pomeranz
2025 J jnl
Direct Search Procedure for Functional Compaction With Improved Fault Coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2025 Misc conf
Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test Sequences.
VTS
Irith Pomeranz
2025 A conf
Functional Logic Diagnosis with Observation Points on Next-State Variables.
ITC
Irith Pomeranz
2025 — conf
Functional Synchronization for Online Testing of Identical Logic Blocks.
DFT
Irith Pomeranz
2025 J jnl
Functionally-Possible Subcircuit-Based Tests for Path Delay Faults.
IEEE Access
Irith Pomeranz
2025 J jnl
Hazard-Based Functionally Possible Transition Faults With High Functional Switching Activities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2025 J jnl
Retry-Based Synchronization for Online Testing of Identical Logic Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2025 J jnl
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2025 J jnl
Sequential Test Generation and Design-for-Testability With Preferred Interconnect Cubes.
IEEE Access
Irith Pomeranz
2025 J jnl
Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive Faults.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2025 Misc conf
Timing-Verification Test Generation Targeting Small Delay Defects.
VTS
Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski
2025 J jnl
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2024 Misc conf
A Storage Based LBIST Scheme for Logic Diagnosis.
VTS
Subashini Gopalsamy, Irith Pomeranz
2024 J jnl
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2024 J jnl
Conventional Tests for Approximate Scan Logic.
IEEE Des. Test
Irith Pomeranz
2024 A conf
Delay Monitoring Under Different PVT Corners for Test and Functional Operation.
ITC
Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024 J jnl
Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2024 J jnl
Functional Compaction for Functional Test Sequences.
IEEE Access
Irith Pomeranz
2024 J jnl
Functional Design-for-Testability for Functional Test Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2024 J jnl
Functionally Possible Path Delay Faults With High Functional Switching Activity.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Yervant Zorian
2024 A conf
Functionally-Possible Gate-Exhaustive Bridging Faults.
ITC
Irith Pomeranz
2024 — conf
Generating Storage-Aware Test Sets Targeting Several Fault Models.
ISVLSI
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
2024 J jnl
Generation of Two-Cycle Tests for Structurally Similar Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024 J jnl
Longest Path Selection Based on Path Identifiers.
IEEE Access
Irith Pomeranz
2024 J jnl
Reduced On-chip Storage of Seeds for Built-in Test Generation.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2024 J jnl
Sharing of Topped-Off Compressed Test Sets Among Logic Blocks.
IEEE Access
Irith Pomeranz
2024 Misc conf
Test Compaction Using (k, 1)-Cycle Tests.
VTS
Irith Pomeranz
2024 J jnl
Test Generation for Functionally Possible Subpaths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2024 J jnl
Test Insertion for Dynamic Test Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2024 J jnl
Testability Evaluation for Local Design Modifications.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2024 J jnl
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2024 J jnl
Unconstrained-Activation Functional-Detection Scan-Based Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2024 J jnl
Weak and Strong Non-Robust Tests for Functionally Possible Path Delay Faults.
IEEE Access
Irith Pomeranz
2023 Misc conf
Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs.
VTS
Irith Pomeranz
2023 A conf
Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines.
ITC
Irith Pomeranz
2023 J jnl
Diagnostic Test Point Insertion and Test Compaction.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2023 J jnl
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2023 J jnl
Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2023 Misc conf
Expanding a Pool of Functional Test Sequences to Support Test Compaction.
VTS
Irith Pomeranz
2023 Misc conf
Fully Deterministic Storage Based Logic Built-In Self-Test.
VTS
Subashini Gopalsamy, Irith Pomeranz
2023 J jnl
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2023 J jnl
Partially Specified Output Response for Reduced Fail Data Volume.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2023 J jnl
Path Unselection for Path Delay Fault Test Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2023 J jnl
Sharing of Compressed Tests Among Logic Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2023 J jnl
Storage and Counter Based Logic Built-In Self-Test.
IEEE Access
Irith Pomeranz
2023 J jnl
Storage-Based Logic Built-In Self-Test With Cyclic Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2023 J jnl
Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2023 J jnl
Test Data Compression for Transparent-Scan Sequences.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2023 J jnl
Topping Off Test Sets Under Bounded Transparent Scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 — conf
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests.
ACM Great Lakes Symposium on VLSI
Hari Addepalli, Irith Pomeranz
2022 — conf
Compaction of Compressed Bounded Transparent-Scan Test Sets.
ACM Great Lakes Symposium on VLSI
Irith Pomeranz
2022 J jnl
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 Misc conf
Fast Test Generation for Structurally Similar Circuits.
VTS
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2022 J jnl
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2022 J jnl
GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 J jnl
Increasing the Fault Coverage of a Truncated Test Set.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2022 J jnl
Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 J jnl
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 J jnl
Preponing Fault Detections for Test Compaction Under Transparent Scan.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2022 — conf
Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines.
ATS
Irith Pomeranz
2022 J jnl
Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 — conf
Storage-Based Logic Built-In Self-Test with Variable-Length Test Data.
DFT
Irith Pomeranz
2022 J jnl
Storage-Based Logic Built-in Self-Test With Multicycle Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2022 A conf
Test Generation for an Iterative Design Flow with RTL Changes.
ITC
Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2022 J jnl
Test Sequences for Faults in the Scan Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2022 A conf
Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models.
ITC
Irith Pomeranz
2022 — conf
Two-Dimensional Test Generation Objective.
ATS
Irith Pomeranz
2022 — conf
Usable Circuits with Imperfect Scan Logic.
ATS
Irith Pomeranz
2022 — conf
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.
ATS
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
2022 J jnl
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2021 Misc conf
Compact Set of LFSR Seeds for Diagnostic Tests.
VTS
Irith Pomeranz
2021 J jnl
Covering Test Holes of Functional Broadside Tests.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2021 J jnl
Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2021 J jnl
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2021 J jnl
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, M. Enamul Amyeen
2021 J jnl
Logic Diagnosis with Hybrid Fail Data.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz, M. Enamul Amyeen
2021 J jnl
Maximal Independent Fault Set for Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2021 J jnl
PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2021 J jnl
Padding of LFSR Seeds for Reduced Input Test Data Volume.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2021 J jnl
Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2021 — conf
Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests.
ATS
Irith Pomeranz
2021 J jnl
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Xijiang Lin
2021 J jnl
Storage-Based Built-In Self-Test for Gate-Exhaustive Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2021 J jnl
Test Compaction by Backward and Forward Extension of Multicycle Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2021 — conf
Zoom-In Feature for Storage-Based Logic Built-In Self-Test.
DFT
Irith Pomeranz
2020 J jnl
Broad-Brush Compaction for Sequential Test Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2020 J jnl
Broadside Tests for Transition and Stuck-At Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 J jnl
Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 J jnl
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2020 J jnl
Functional Broadside Tests Under Broadcast Scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 J jnl
Globally Functional Transparent-Scan Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 — conf
Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults.
DFT
Irith Pomeranz
2020 Misc conf
Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs.
VTS
Irith Pomeranz
2020 J jnl
LFSR-Based Test Generation for Reduced Fail Data Volume.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Srikanth Venkataraman
2020 J jnl
LFSR-based generation of boundary-functional broadside tests.
IET Comput. Digit. Tech.
Irith Pomeranz
2020 J jnl
Multicycle Broadside and Skewed-Load Tests for Test Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 J jnl
New Targets for Diagnostic Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 Misc conf
Non-Masking Non-Robust Tests for Path Delay Faults.
VTS
Irith Pomeranz
2020 J jnl
RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2020 C conf
Reduced Fault Coverage as a Target for Design Scaffolding Security.
IOLTS
Irith Pomeranz, Sandip Kundu
2020 J jnl
Reverse Low-Power Broadside Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 A conf
Selecting Close-to-Functional Path Delay Faults for Test Generation.
ITC
Irith Pomeranz
2020 J jnl
Selection of Primary Output Vectors to Observe Under Multicycle Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2020 C conf
Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests.
IOLTS
Irith Pomeranz
2020 J jnl
Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2020 J jnl
Target Faults for Test Compaction Based on Multicycle Tests.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2019 J jnl
Boundary-Functional Broadside and Skewed-Load Tests.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2019 A conf
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation.
ITC
Irith Pomeranz
2019 J jnl
Diagnostic Test Generation That Addresses Diagnostic Holes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2019 J jnl
Extended Transparent-Scan.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2019 J jnl
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2019 J jnl
Incomplete Tests for Undetectable Faults to Improve Test Set Quality.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2019 J jnl
Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2019 A conf
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults.
ITC
Irith Pomeranz
2019 J jnl
LFSR-Based Test Generation for Path Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2019 J jnl
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst.
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019 Misc conf
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults.
VTS
Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman
2019 J jnl
Padding of Multicycle Broadside and Skewed-Load Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2019 A conf
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
DATE
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019 J jnl
Skewed-Load Tests for Transition and Stuck-at Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2019 — conf
TEA: A Test Generation Algorithm for Designs with Timing Exceptions.
ATS
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
2019 Misc conf
Test Compaction Under Bounded Transparent-Scan.
VTS
Irith Pomeranz
2019 J jnl
Test Compaction by Test Removal Under Transparent Scan.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2019 J jnl
Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2019 J jnl
Updating the sets of target faults during test generation for multiple fault models.
IET Comput. Digit. Tech.
Irith Pomeranz
2018 J jnl
An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2018 J jnl
Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2018 B conf
Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests.
ETS
Irith Pomeranz
2018 J jnl
Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2018 J jnl
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2018 — conf
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests.
DFT
Naixing Wang, Irith Pomeranz, Brady Benware, M. Enamul Amyeen, Srikanth Venkataraman
2018 B conf
Interconnect-aware tests to complement gate-exhaustive tests.
ETS
Irith Pomeranz, Srikanth Venkataraman
2018 J jnl
Observation Points on State Variables for the Compaction of Multicycle Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2018 A conf
On Close-to-Functional Test Sequences.
ITC
Irith Pomeranz
2018 J jnl
On-chip generation of primary input sequences for multicycle functional broadside tests.
IET Comput. Digit. Tech.
Irith Pomeranz
2018 J jnl
Partially Invariant Patterns for
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2018 — conf
Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set.
DFT
Irith Pomeranz
2018 J jnl
Selecting Functional Test Sequences for Defect Diagnosis.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2018 J jnl
Static test compaction procedure for large pools of multicycle functional broadside tests.
IET Comput. Digit. Tech.
Irith Pomeranz
2017 A conf
A bridging fault model for line coverage in the presence of undetected transition faults.
DATE
Irith Pomeranz
2017 J jnl
Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2017 J jnl
Close-to-Functional Broadside Tests With a Safety Margin.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2017 — conf
Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults.
ATS
Irith Pomeranz
2017 J jnl
Computation of Seeds for
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2017 Misc conf
Fail data reduction for diagnosis of scan chain faults under transparent-scan.
VTS
Irith Pomeranz
2017 — conf
Functional Broadside Test Generation Using a Commercial ATPG Tool.
ISVLSI
Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz
2017 J jnl
Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2017 J jnl
Identifying Biases of a Defect Diagnosis Procedure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2017 J jnl
LFSR-Based Generation of Multicycle Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2017 J jnl
Metric for the ability of functional capture cycles to ensure functional operation conditions.
IET Comput. Digit. Tech.
Irith Pomeranz
2017 J jnl
New Techniques to Reduce the Execution Time of Functional Test Programs.
IEEE Trans. Computers
Marco Gaudesi, Irith Pomeranz, Matteo Sonza Reorda, Giovanni Squillero
2017 A conf
POSTT: Path-oriented static test compaction for transition faults in scan circuits.
ITC
Irith Pomeranz
2017 J jnl
Reconstruction of a functional test sequence for increased fault coverage.
IET Comput. Digit. Tech.
Irith Pomeranz
2017 J jnl
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
Shraddha Bodhe, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman
2017 J jnl
Restoration-Based Merging of Functional Test Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2017 J jnl
Selecting Replacements for Undetectable Path Delay Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2017 A conf
Selecting target bridging faults for uniform circuit coverage.
ITC
Irith Pomeranz
2017 J jnl
Sequential Test Generation Based on Preferred Primary Input Cubes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2017 — conf
Static Compaction by Merging of Seeds for LFSR-Based Test Generation.
ISVLSI
Irith Pomeranz
2017 — conf
Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites.
ATS
Irith Pomeranz
2017 J jnl
Test Modification for Reduced Volumes of Fail Data.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman
2017 A conf
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure.
ITC
Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen
2017 Misc conf
Using piecewise-functional broadside tests for functional broadside test compaction.
VTS
Irith Pomeranz
2016 — conf
A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set.
ISVLSI
Irith Pomeranz
2016 — conf
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction.
ATS
M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman
2016 J jnl
A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2016 Misc conf
A convergent procedure for partially-reachable states.
VTS
Irith Pomeranz
2016 J jnl
Balancing the Numbers of Detected Faults for Improved Test Set Quality.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2016 J jnl
Combined input test data volume reduction for mixed broadside and skewed-load test sets.
IET Comput. Digit. Tech.
Irith Pomeranz
2016 J jnl
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2016 J jnl
Design-for-Testability for Functional Broadside Tests under Primary Input Constraints.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2016 J jnl
Diagnostic Fail Data Minimization Using an N-Cover Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Shraddha Bodhe, M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman
2016 J jnl
Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults.
IEEE Trans. Computers
Irith Pomeranz
2016 J jnl
Improving the accuracy of defect diagnosis by adding and removing tests.
IET Comput. Digit. Tech.
Irith Pomeranz
2016 J jnl
LFSR-Based Generation of Partially-Functional Broadside Tests.
IEEE Trans. Computers
Irith Pomeranz
2016 — conf
On the Switching Activity in Faulty Circuits During Test Application.
ATS
Irith Pomeranz, Sudhakar M. Reddy
2016 J jnl
Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2016 Misc conf
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm.
VTS
Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman
2016 J jnl
Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2016 J jnl
Static test compaction for circuits with multiple independent scan chains.
IET Comput. Digit. Tech.
Irith Pomeranz
2015 J jnl
A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2015 J jnl
A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2015 Misc conf
A definition of the number of detections for faults with single tests in a compact scan-based test set.
VTS
Irith Pomeranz
2015 J jnl
Computation of Seeds for LFSR-Based Diagnostic Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2015 J jnl
Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2015 J jnl
FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2015 A* conf
FaultHound: value-locality-based soft-fault tolerance.
ISCA
Nitin, Irith Pomeranz, T. N. Vijaykumar
2015 A* conf
Generation of close-to-functional broadside tests with equal primary input vectors.
DAC
Irith Pomeranz
2015 Misc conf
Improving the accuracy of defect diagnosis by considering reduced diagnostic information.
VTS
Irith Pomeranz
2015 J jnl
Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2015 B conf
On test program compaction.
ETS
Marco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz
2015 J jnl
Piecewise-Functional Broadside Tests Based on Reachable States.
IEEE Trans. Computers
Irith Pomeranz
2015 — conf
Piecewise-functional broadside tests based on intersections of reachable states.
DFTS
Irith Pomeranz
2015 — conf
Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence.
ISVLSI
Irith Pomeranz
2015 J jnl
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2015 J jnl
Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2015 J jnl
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2015 J jnl
Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences.
IEEE Trans. Computers
Irith Pomeranz
2015 Misc conf
Test compaction by test cube merging for four-way bridging faults.
VTS
Irith Pomeranz
2015 Misc conf
Test vector omission with minimal sets of simulated faults.
VTS
Irith Pomeranz
2015 J jnl
Two-Dimensional Static Test Compaction for Functional Test Sequences.
IEEE Trans. Computers
Irith Pomeranz
2015 J jnl
Use of input necessary assignments for test generation based on merging of test cubes.
IET Comput. Digit. Tech.
Irith Pomeranz
2014 B conf
A distance-based test cube merging procedure for compatible and incompatible test cubes.
ETS
Irith Pomeranz
2014 — conf
Built-in generation of functional broadside tests considering primary input constraints.
ACM Great Lakes Symposium on VLSI
Bo Yao, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen
2014 J jnl
Design-for-testability for multi-cycle broadside tests by holding of state variables.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2014 — conf
FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes.
ISVLSI
Irith Pomeranz
2014 Misc conf
Fault simulation with test switching for static test compaction.
VTS
Irith Pomeranz
2014 J jnl
Functional Broadside Tests for Multistep Defect Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2014 J jnl
Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2014 Misc conf
Innovative practices session 10C: Advances in DFT and compression.
VTS
Rohit Kapur, Irith Pomeranz
2014 J jnl
Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2014 J jnl
Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2014 J jnl
Low-Power Test Generation by Merging of Functional Broadside Test Cubes.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2014 J jnl
Low-power skewed-load tests based on functional broadside tests.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2014 J jnl
Multi-cycle broadside tests with runs of constant primary input vectors.
IET Comput. Digit. Tech.
Irith Pomeranz
2014 — conf
OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis.
ISVLSI
Irith Pomeranz
2014 Misc conf
On the use of multi-cycle tests for storage of two-cycle broadside tests.
VTS
Irith Pomeranz
2014 J jnl
Reducing the input test data volume under transparent scan.
IET Comput. Digit. Tech.
Irith Pomeranz
2014 J jnl
Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2014 J jnl
Selection of Functional Test Sequences With Overlaps.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2014 J jnl
Sharing Logic for Built-In Generationof Functional Broadside Tests.
IEEE Trans. Computers
Irith Pomeranz
2014 J jnl
Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2014 J jnl
Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2014 A conf
Substituting transition faults with path delay faults as a basic delay fault model.
DATE
Irith Pomeranz
2014 J jnl
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2014 A conf
Test and non-test cubes for diagnostic test generation based on merging of test cubes.
DATE
Irith Pomeranz
2014 J jnl
Unknown Output Values of Faulty Circuits and Output Response Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2013 J jnl
An Adjacent Switching Activity Metric under Functional Broadside Tests.
IEEE Trans. Computers
Irith Pomeranz
2013 J jnl
Broadside and Skewed-Load Tests Under Primary Input Constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2013 J jnl
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2013 J jnl
Built-in generation of multicycle functional broadside tests with observation points.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz
2013 — conf
Classes of difficult-to-diagnose transition fault clusters.
DFTS
Irith Pomeranz
2013 J jnl
Computing Two-Pattern Test Cubes for Transition Path Delay Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2013 J jnl
Diagnostic Test Sets with Increased Switching Activity for Transition Faults.
J. Low Power Electron.
Irith Pomeranz
2013 J jnl
Functional Broadside Templates for Low-Power Test Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2013 J jnl
Functional Broadside Tests With Incompletely Specified Scan-In States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2013 J jnl
Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2013 B conf
Generation of compact multi-cycle diagnostic test sets.
ETS
Irith Pomeranz
2013 J jnl
Low-power test sets under test-related primary input constraints.
Int. J. Crit. Comput. Based Syst.
Irith Pomeranz
2013 J jnl
Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2013 J jnl
On Test Compaction of Broadside and Skewed-Load Test Cubes.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2013 A conf
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes.
DATE
Irith Pomeranz
2013 J jnl
On multi-cycle test cubes.
IET Comput. Digit. Tech.
Irith Pomeranz
2013 Misc conf
Path selection based on static timing analysis considering input necessary assignments.
VTS
Bo Yao, Arani Sinha, Irith Pomeranz
2013 J jnl
Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2013 J jnl
Signal-Transition Patterns of Functional Broadside Tests.
IEEE Trans. Computers
Irith Pomeranz
2013 J jnl
Static test compaction for mixed broadside and skewed-load transition fault test sets.
IET Comput. Digit. Tech.
Irith Pomeranz
2013 J jnl
Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2012 J jnl
A Metric for Identifying Detectable Path Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2012 — conf
Built-in generation of multi-cycle broadside tests.
DFT
Irith Pomeranz
2012 J jnl
Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length.
IEEE Trans. Computers
Irith Pomeranz
2012 J jnl
Fast Identification of Undetectable Transition Faults under Functional Broadside Tests.
IEEE Trans. Computers
Irith Pomeranz
2012 J jnl
Functional broadside tests for embedded logic blocks.
IET Comput. Digit. Tech.
Irith Pomeranz
2012 — conf
Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults.
DFT
Irith Pomeranz
2012 J jnl
Generation of Mixed Test Sets for Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2012 J jnl
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2012 — conf
Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests.
DFT
Irith Pomeranz
2012 J jnl
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2012 J jnl
Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2012 J jnl
Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2012 J jnl
Non-Uniform Coverage by n -Detection Test Sets.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz
2012 J jnl
On the Computation of Common Test Data for Broadside and Skewed-Load Tests.
IEEE Trans. Computers
Irith Pomeranz
2012 J jnl
On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests.
IEEE Trans. Computers
Irith Pomeranz
2012 B conf
On the detection of path delay faults by functional broadside tests.
ETS
Irith Pomeranz
2012 — conf
Performance aware partitioning for 3D-SOCs.
ISOCC
Amit Kumar, Sudhakar M. Reddy, Bernd Becker, Irith Pomeranz
2012 J jnl
Reset and partial-reset-based functional broadside tests.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2012 J jnl
Resolution of Diagnosis Based on Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2012 Misc conf
Static test compaction for transition faults under the hazard-based detection conditions.
VTS
Irith Pomeranz
2012 — conf
TSV and DFT cost aware circuit partitioning for 3D-SOCs.
ISQED
Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2012 J jnl
Test vector chains for increased resolution and reduced storage of diagnostic tests.
IET Comput. Digit. Tech.
Irith Pomeranz
2012 J jnl
Undetectable transition faults under broadside tests with constant primary input vectors.
IET Comput. Digit. Tech.
Irith Pomeranz
2011 C conf
Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity.
PRDC
Irith Pomeranz
2011 J jnl
Broadside and Functional Broadside Tests for Partial-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 A conf
Built-in generation of functional broadside tests.
DATE
Irith Pomeranz
2011 A* conf
Diagnosis of transition fault clusters.
DAC
Irith Pomeranz
2011 — conf
Fault diagnosis aware ATE assisted test response compaction.
ASP-DAC
J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011 J jnl
Fixed-State Tests for Delay Faults in Scan Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 C conf
Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults.
PRDC
Irith Pomeranz
2011 J jnl
Generation of Multi-Cycle Broadside Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2011 A conf
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing.
DATE
Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011 J jnl
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 C conf
Max-Fill: A method to generate high quality delay tests.
DDECS
Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz
2011 J jnl
On Functional Broadside Tests With Functional Propagation Conditions.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 B conf
On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests.
ETS
Irith Pomeranz
2011 Misc conf
On clustering of undetectable transition faults in standard-scan circuits.
VTS
Irith Pomeranz
2011 J jnl
Primary input cones based on test sequences in synchronous sequential circuits.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Reducing the switching activity of test sequences under transparent-scan.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Scan Shift Power of Functional Broadside Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2011 J jnl
Sizes of test sets for path delay faults using strong and weak non-robust tests.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 Misc conf
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests.
VTS
Irith Pomeranz
2011 J jnl
Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2011 J jnl
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan.
J. Low Power Electron.
Irith Pomeranz, Sudhakar M. Reddy
2011 J jnl
Two-dimensional partially functional broadside tests.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2010 Misc conf
Defect diagnosis based on DFM guidelines.
VTS
Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman
2010 — conf
Deterministic broadside test generation for transition path delay faults.
ACM Great Lakes Symposium on VLSI
Bo Yao, Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Diagnosis of path delay faults based on low-coverage tests.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2010 Misc conf
Forming multi-cycle tests for delay faults by concatenating broadside tests.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2010 — conf
Functional and partially-functional skewed-load tests.
ASP-DAC
Irith Pomeranz, Sudhakar M. Reddy
2010 — conf
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 Misc conf
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2010 B conf
Input test data volume reduction based on test vector chains.
ETS
Irith Pomeranz, Sudhakar M. Reddy
2010 A conf
Multiple fault activation cycle tests for transistor stuck-open faults.
ITC
Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz
2010 — conf
On Bias in Transition Coverage of Test Sets for Path Delay Faults.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
On Test Generation With Test Vector Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
On Undetectable Faults and Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 Misc conf
On multiple bridging faults.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2010 A conf
On reset based functional broadside tests.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2010 Misc conf
Output-Dependent Diagnostic Test Generation.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Path Selection for Transition Path Delay Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 A conf
Reducing the storage requirements of a test sequence by using a background vector.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 C conf
Selecting state variables for improved on-line testability through output response comparison of identical circuits.
IOLTS
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Static test compaction for diagnostic test sets of full-scan circuits.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Switching Activity as a Test Compaction Heuristic for Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
TOV: Sequential Test Generation by Ordering of Test Vectors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2010 J jnl
Test Sequences with Reduced and Increased Switching Activity.
J. Low Power Electron.
Irith Pomeranz, Sudhakar M. Reddy
2009 A conf
A scalable method for the generation of small test sets.
DATE
Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz
2009 — conf
Definition and application of approximate necessary assignments.
ACM Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Definition and generation of partially-functional broadside tests.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
Detectability of internal bridging faults in scan chains.
ASP-DAC
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2009 J jnl
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
Dynamic test compaction for a random test generation procedure with input cube avoidance.
ASP-DAC
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
Fault Diagnosis under Transparent-Scan.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
Improving the Detectability of Resistive Open Faults in Scan Cells.
DFT
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2009 B conf
Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation.
ETS
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
N-distinguishing Tests for Enhanced Defect Diagnosis.
Asian Test Symposium
Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz
2009 — conf
On-chip Generation of the Second Primary Input Vectors of Broadside Tests.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
Partitioned n-detection test generation.
ACM Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Random Test Generation With Input Cube Avoidance.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2009 A conf
Selection of a fault model for fault diagnosis based on unique responses.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits.
IEEE Trans. Dependable Secur. Comput.
Irith Pomeranz, Sudhakar M. Reddy
2009 — conf
State persistence: a property for guiding test generation.
ACM Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Test compaction methods for transition faults under transparent-scan.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Test vector chains for increasing the fault coverage and numbers of detections.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2009 Misc conf
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2009 J jnl
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2008 A conf
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2008 A conf
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2008 — conf
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
DFT
Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz
2008 C conf
An Enhanced Logic BIST Architecture for Online Testing.
IOLTS
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008 — conf
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
ASP-DAC
Irith Pomeranz, Sudhakar M. Reddy
2008 Misc conf
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2008 Misc conf
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2008 A conf
Detection of Internal Stuck-open Faults in Scan Chains.
ITC
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008 — conf
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
DFT
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008 Misc conf
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2008 J jnl
Functional Broadside Tests with Minimum and Maximum Switching Activity.
J. Low Power Electron.
Irith Pomeranz, Sudhakar M. Reddy
2008 J jnl
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2008 Misc conf
On Common-Mode Skewed-Load and Broadside Tests.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2008 J jnl
On Complete Functional Broadside Tests for Transition Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
2008 — conf
On Reducing Circuit Malfunctions Caused by Soft Errors.
DFT
Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker
2008 A* conf
On tests to detect via opens in digital CMOS circuits.
DAC
Sudhakar M. Reddy, Irith Pomeranz, Chen Liu
2008 Misc conf
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.
VTS
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
2008 J jnl
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2008 J jnl
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2008 — conf
Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects.
ATS
Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman
2008 B conf
Safe Fault Collapsing Based on Dominance Relations.
ETS
Irith Pomeranz, Sudhakar M. Reddy
2008 J jnl
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2008 Misc conf
Synthesis for Broadside Testability of Transition Faults.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2008 — conf
Test vector chains for increased targeted and untargeted fault coverage.
ASP-DAC
Irith Pomeranz, Sudhakar M. Reddy
2008 J jnl
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2008 J jnl
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2007 — conf
A-Diagnosis: A Complement to Z-Diagnosis.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2007 Misc conf
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2007 B conf
Diagnostic Test Generation Based on Subsets of Faults.
ETS
Irith Pomeranz, Sudhakar M. Reddy
2007 — conf
Diagnostic Test Generation Targeting Equivalence Classes.
ATS
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
Effectiveness of scan-based delay fault tests in diagnosis of transition faults.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2007 — conf
Enhanced Broadside Testing for Improved Transition Fault Coverage.
ATS
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
Enhancing delay fault coverage through low-power segmented scan.
IET Comput. Digit. Tech.
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2007 Misc conf
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2007 — conf
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation.
ATS
Irith Pomeranz, Praveen Parvathala, Srinivas Patil
2007 J jnl
Forming N-detection test sets without test generation.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2007 Misc conf
Functional Broadside Tests with Different Levels of Reachability.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
Invariant States and Redundant Logic in Synchronous Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2007 Misc conf
Low Shift and Capture Power Scan Tests.
VLSI Design
Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007 A conf
On test generation by input cube avoidance.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2007 A conf
On the saturation of n-detection test sets with increased n.
ITC
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
Scan-Based Tests with Low Switching Activity.
IEEE Des. Test Comput.
Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007 — conf
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2007 A conf
Testing for systematic defects based on DFM guidelines.
ITC
Dongok Kim, M. Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau
2007 J jnl
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
CoRR
Irith Pomeranz, Sudhakar M. Reddy
2007 — conf
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.
ASP-DAC
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
2007 J jnl
Worst-Case and Average-Case Analysis of n-Detection Test Sets
CoRR
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
Worst-case and average-case analysis of n-detection test sets and test generation strategies.
IET Comput. Digit. Tech.
Irith Pomeranz, Sudhakar M. Reddy
2007 J jnl
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman
2006 A conf
A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.
ITC
Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz
2006 — conf
A Functional Fault Model with Implicit Fault Effect Propagation Requirements.
ATS
Irith Pomeranz, Srinivas Patil, Praveen Parvathala
2006 C conf
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.
IOLTS
Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2006 Misc conf
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults.
VTS
Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
2006 B conf
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
ETS
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2006 A conf
A delay fault model for at-speed fault simulation and test generation.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
2006 A* conf
A test pattern ordering algorithm for diagnosis with truncated fail data.
DAC
Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006 Misc conf
Dominance Based Analysis for Large Volume Production Fail Diagnosis.
VTS
Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy
2006 B conf
Enhancing Delay Fault Coverage through Low Power Segmented Scan.
ETS
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2006 B conf
Fault Collapsing for Transition Faults Using Extended Transition Faults.
ETS
Irith Pomeranz, Sudhakar M. Reddy
2006 A conf
Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences.
ITC
Irith Pomeranz, Sudhakar M. Reddy
2006 J jnl
Generation of Functional Broadside Tests for Transition Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2006 A conf
Generation of broadside transition fault test sets that detect four-way bridging faults.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2006 J jnl
Improved n-Detection Test Sequences Under Transparent Scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2006 Misc conf
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.
VLSI Design
Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006 J jnl
On Finding Don't Cares in Test Sequences for Sequential Circuits.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu
2006 J jnl
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2006 — conf
On the Replacement of Scan Chain Inputs by Primary Input Vectors.
ATS
Irith Pomeranz, Sudhakar M. Reddy
2006 — conf
On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits.
V&D@FLoC
Irith Pomeranz, Sudhakar M. Reddy
2006 A conf
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.
ITC
Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006 Misc conf
Scan Tests with Multiple Fault Activation Cycles for Delay Faults.
VTS
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2006 J jnl
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2006 — conf
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2006 — conf
Selecting High-Quality Delay Tests for Manufacturing Test and Debug.
DFT
Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
2006 — conf
Test Generation for Open Defects in CMOS Circuits.
DFT
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2006 A conf
Test compaction for transition faults under transparent-scan.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2006 Misc conf
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2006 — conf
To Overtest Or Not To Overtest - More Questions Than Answers.
ATS
Irith Pomeranz
2006 J jnl
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2006 J jnl
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2005 C conf
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
ICCD
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2005 B conf
A unified fault model and test generation procedure for interconnect opens and bridges.
ETS
Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
2005 J jnl
Autoscan: a scan design without external scan inputs or outputs.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2005 — conf
Battery-aware dynamic voltage scaling in multiprocessor embedded system.
ISCAS (1)
Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi
2005 — conf
Circuit Independent Weighted Pseudo-Random BIST Pattern Generator.
Asian Test Symposium
Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2005 J jnl
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors.
IEEE Trans. Dependable Secur. Comput.
Irith Pomeranz, Sudhakar M. Reddy
2005 A conf
Defect Aware Test Patterns.
DATE
Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz
2005 — conf
Dynamic Test Compaction for Bridging Faults.
ISQED
Irith Pomeranz, Sudhakar M. Reddy
2005 — conf
Fault Diagnosis and Fault Model Aliasing.
ISVLSI
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
2005 A conf
Forming N-detection test sets from one-detection test sets without test generation.
ITC
Irith Pomeranz, Sudhakar M. Reddy
2005 — conf
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Asian Test Symposium
Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz
2005 A conf
Methods for improving transition delay fault coverage using broadside tests.
ITC
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2005 A* conf
N-detection under transparent-scan.
DAC
Irith Pomeranz
2005 Misc conf
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
VLSI Design
Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
2005 — conf
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.
DFT
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
2005 — conf
On Reducing Peak Current and Power during Test.
ISVLSI
Wei Li, Sudhakar M. Reddy, Irith Pomeranz
2005 J jnl
On fault equivalence, fault dominance, and incompletely specified test sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2005 J jnl
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2005 J jnl
On reducing test application time for scan circuits using limited scan operations and transfer sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
2005 B conf
Path-oriented transition fault test generation considering operating conditions.
ETS
Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2005 — conf
Recovery During Concurrent On-Line Testing of Identical Circuits.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2005 A conf
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2005 Misc conf
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2005 B conf
Using dummy bridging faults to define a reduced set of target faults.
ETS
Irith Pomeranz, Sudhakar M. Reddy
2005 A conf
Worst-Case and Average-Case Analysis of n-Detection Test Sets.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
A Measure of Quality for n-Detection Test Sets.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2004 — conf
A Postprocessing Procedure of Test Enrichment for Path Delay Faults.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2004 — conf
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
Constrained test generation for embedded synchronous sequential circuits with serial-input access.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2004 Misc conf
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.
VLSI Design
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen
2004 J jnl
Don't Care Identification and Statistical Encoding for Test Data Compression.
IEICE Trans. Inf. Syst.
Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
Fault isolation for nonisolated blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Yervant Zorian
2004 J jnl
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2004 A conf
Level of Similarity: A Metric for Fault Collapsing.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers
Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2004 Misc conf
On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2004 C conf
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2004 A* conf
On test generation for transition faults with minimized peak power dissipation.
DAC
Wei Li, Sudhakar M. Reddy, Irith Pomeranz
2004 J jnl
On the characterization and efficient computation of hard-to-detect bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2004 A* conf
On the generation of scan-based test sets with reachable states for testing under functional operation conditions.
DAC
Irith Pomeranz
2004 — conf
Properties of Maximally Dominating Faults.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2004 — conf
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.
DFT
Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2004 — conf
Scan BIST Targeting Transition Faults Using a Markov Source.
ISQED
Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
2004 A* conf
Scan-BIST based on transition probabilities.
DAC
Irith Pomeranz
2004 J jnl
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2004 — conf
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.
ISQED
Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
2004 J jnl
Vector-restoration-based static compaction using random initial omission.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2004 — conf
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.
Asian Test Symposium
Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2004 A conf
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
ITC
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
2004 A conf
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis.
DATE
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri
2003 — conf
A DFT Approach for Path Delay Faults in Interconnected Circuits.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2003 J jnl
A Low Power Pseudo-Random BIST Technique.
J. Electron. Test.
Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2003 C conf
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.
ICCD
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
2003 A conf
A New Approach to Test Generation and Test Compaction for Scan Circuits.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2003 Misc conf
A Test Interface for Built-In Test of Non-Isolated Scanned Cores.
VTS
Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian
2003 A* conf
A scan BIST generation method using a markov source and partial bit-fixing.
DAC
Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
2003 C conf
An Improved Markov Source Design for Scan BIST.
IOLTS
Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz
2003 Misc conf
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.
VTS
Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz
2003 J jnl
Fault equivalence identification in combinational circuits using implication and evaluation techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
2003 Misc conf
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
VLSI Design
Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz
2003 A conf
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
2003 A conf
On Compacting Test Response Data Containing Unknown Values.
ICCAD
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
2003 Misc conf
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2003 A conf
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.
ITC
Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz
2003 J jnl
On Selecting Testable Paths in Scan Designs.
J. Electron. Test.
Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2003 — conf
On path selection for delay fault testing considering operating conditions [logic IC testing].
ETW
Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003 A* conf
On test data compression and n-detection test sets.
DAC
Irith Pomeranz, Sudhakar M. Reddy
2003 J jnl
On test data volume reduction for multiple scan chain designs.
ACM Trans. Design Autom. Electr. Syst.
Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2003 A conf
On the Characterization of Hard-to-Detect Bridging Faults.
DATE
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003 A conf
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.
ITC
Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003 — conf
Optimizing SOC Test Resources Using Dual Sequences.
VLSI-SoC (Selected Papers)
Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz
2003 C conf
Optimizing SOC Test Resources using Dual Sequences.
VLSI-SOC
Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz
2003 J jnl
PROPTEST: a property-based test generator for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
2003 C conf
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.
ICCD
Gang Chen, Sudhakar M. Reddy, Irith Pomeranz
2003 A conf
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains.
ITC
Irith Pomeranz
2003 J jnl
Reverse-order-restoration-based static test compaction for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
2003 Misc conf
SOC Test Scheduling Using Simulated Annealing.
VTS
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang
2003 Misc conf
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2003 C conf
Static Test Compaction for Multiple Full-Scan Circuits.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2003 A conf
Test Data Compression Based on Output Dependence.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2003 — conf
Test Data Volume Reduction by Test Data Realignment.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2003 J jnl
Test data compression based on input-output dependence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2003 J jnl
Test enrichment for path delay faults using multiple sets of target faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2003 J jnl
Theorems for identifying undetectable faults in partial-scan circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2003 A* conf
Transient-Fault Recovery for Chip Multiprocessors.
ISCA
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar
2003 J jnl
Transient-Fault Recovery for Chip Multiprocessors.
IEEE Micro
Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz
2003 J jnl
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2002 C conf
A Low Power Pseudo-Random BIST Technique.
ICCD
Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002 — conf
A Low Power Pseudo-Random BIST Technique.
IOLTW
Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002 — conf
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2002 — conf
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.
ASP-DAC/VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2002 J jnl
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2002 J jnl
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2002 A conf
Conflict driven techniques for improving deterministic test pattern generation.
ICCAD
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2002 C conf
Don't-Care Identification on Specific Bits of Test Patterns.
ICCD
Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
2002 J jnl
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2002 — conf
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Asian Test Symposium
Ilia Polian, Irith Pomeranz, Bernd Becker
2002 A conf
Fault Isolation Using Tests for Non-Isolated Blocks.
DATE
Irith Pomeranz, Yervant Zorian
2002 A conf
Finding a Common Fault Response for Diagnosis during Silicon Debug.
DATE
Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy
2002 — conf
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2002 — conf
On Generating High Quality Tests for Transition Faults.
Asian Test Symposium
Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
2002 Misc conf
On Test Data Volume Reduction for Multiple Scan Chain Designs.
VTS
Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2002 A conf
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
ITC
Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
2002 A* conf
On output response compression in the presence of unknown output values.
DAC
Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2002 — conf
On selecting testable paths in scan designs.
ETW
Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2002 C conf
On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2002 J jnl
On the use of random limited-scan to improve at-speed randompattern testing of scan circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz
2002 A conf
On undetectable faults in partial scan circuits.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
2002 — conf
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples.
ASP-DAC/VLSI Design
Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
2002 — conf
Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits.
DELTA
Irith Pomeranz, Sudhakar M. Reddy
2002 J jnl
Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2002 A conf
Pseudo Random Patterns Using Markov Sources for Scan BIST.
ITC
Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
2002 — conf
Test Data Compression Using Don't-Care Identification and Statistical Encoding.
DELTA
Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy
2002 — conf
Test Data Compression Using Don?t-Care Identification and Statistical Encoding.
Asian Test Symposium
Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
2002 A conf
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2002 J jnl
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2002 Misc conf
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits.
VTS
M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs
2002 A* conf
Transient-Fault Recovery Using Simultaneous Multithreading.
ISCA
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
2002 J jnl
n-pass n-detection fault simulation and its applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2001 C conf
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2001 — conf
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2001 J jnl
A built-in self-test method for diagnosis of synchronous sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2001 A conf
A method to enhance the fault coverage obtained by output response comparison of identical circuits.
ITC
Irith Pomeranz, Sudhakar M. Reddy
2001 A* conf
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing.
DAC
Irith Pomeranz, Sudhakar M. Reddy
2001 — conf
An Efficient Method to Identify Untestable Path Delay Faults.
Asian Test Symposium
Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz
2001 C conf
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2001 A conf
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2001 J jnl
Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits.
J. Syst. Archit.
Irith Pomeranz, Sudhakar M. Reddy
2001 — conf
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description.
HLDVT
Irith Pomeranz, Sudhakar M. Reddy
2001 — conf
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin
2001 Misc conf
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.
VTS
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
2001 J jnl
Forward-looking fault simulation for improved static compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2001 — conf
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits.
ACM Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
2001 Misc conf
On Improving Static Test Compaction for Sequential Circuits.
VLSI Design
Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
2001 — conf
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits.
Asian Test Symposium
Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
2001 — conf
On Pass/Fail Dictionaries for Scan Circuits .
Asian Test Symposium
Irith Pomeranz
2001 J jnl
On diagnosis and diagnostic test generation for pattern-dependenttransition faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2001 A conf
On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
ITC
Irith Pomeranz, Sudhakar M. Reddy
2001 A conf
On static test compaction and test pattern ordering for scan designs.
ITC
Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
2001 Misc conf
On the Use of Fault Dominance in n-Detection Test Generation.
VTS
Irith Pomeranz, Sudhakar M. Reddy
2001 A conf
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits.
ICCAD
Chen Wang, Irith Pomeranz, Sudhakar M. Reddy
2001 A* conf
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits.
DAC
Irith Pomeranz
2001 J jnl
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
2001 A conf
Sequence reordering to improve the levels of compaction achievable by static compaction procedures.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2001 J jnl
Testing of scan circuits containing nonisolated random-logic legacycores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Y. Zonan
2001 J jnl
Vector replacement to improve static-test compaction forsynchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2000 J jnl
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2000 — conf
Enhanced untestable path analysis using edge graphs.
Asian Test Symposium
Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy
2000 C conf
Fault diagnosis based on parameters of output responses.
PRDC
Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
Functional Test Generation for Full Scan Circuits.
DATE
Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
Improving the Proportion of At-Speed Tests in Scan BIST.
ICCAD
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski
2000 J jnl
On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2000 Misc conf
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
2000 C conf
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2000 A* conf
On diagnosis of pattern-dependent delay faults.
DAC
Irith Pomeranz, Sudhakar M. Reddy
2000 J jnl
On n-detection test sets and variable n-detection test sets fortransition faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2000 J jnl
On synchronizable circuits and their synchronizing sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
2000 J jnl
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2000 — conf
On the feasibility of fault simulation using partial circuit descriptions.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2000 — conf
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits.
ETW
Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
On validating data hold times for flip-flops in sequential circuits.
ITC
Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
2000 J jnl
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
2000 — conf
Reducing test application time for full scan circuits by the addition of transfer sequences.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
2000 Misc conf
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
VTS
Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
Selection of potentially testable path delay faults for test generation.
ITC
Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
2000 C conf
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
Simulation Based Test Generation for Scan Designs.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
2000 J jnl
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
J. Electron. Test.
Irith Pomeranz, Sudhakar M. Reddy
2000 Misc conf
Test Transformation to Improve Compaction by Statistical Encoding.
VLSI Design
Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
2000 A conf
Test-Point Insertion to Enhance Test Compaction for Scan Designs.
DSN
Irith Pomeranz, Sudhakar M. Reddy
1999 J jnl
A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1999 Misc conf
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits.
VTS
Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
1999 Misc conf
A Flexible Path Selection Procedure for Path Delay Fault Testing.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1999 J jnl
A comment on "Improving a nonenumerative method to estimate path delay fault coverage".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1999 A conf
An approach for improving the levels of compaction achieved by vector omission.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1999 A* conf
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1999 C conf
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
1999 A conf
Full Scan Fault Coverage With Partial Scan.
DATE
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1999 Misc conf
Implication and Evaluation Techniques for Proving Fault Equivalence.
VTS
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
1999 A conf
On achieving complete coverage of delay faults in full scan circuits using locally available lines.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1999 — conf
On avoiding undetectable faults during test generation.
ETW
Irith Pomeranz, Sudhakar M. Reddy
1999 Misc conf
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1999 — conf
PASTA: Partial Scan to Enhance Test Compaction.
Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
1999 — conf
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1999 Misc conf
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
VTS
Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin
1999 A* conf
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction.
DAC
Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
1999 J jnl
Static test compaction for synchronous sequential circuits based on vector restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo
1999 A conf
Techniques for improving the efficiency of sequential circuit test generation.
ICCAD
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1999 Misc conf
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic.
VTS
Irith Pomeranz, Yervant Zorian
1999 A conf
The effects of test compaction on fault diagnosis.
ITC
Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
1999 Misc conf
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1999 — conf
Vector-Based Functional Fault Models for Delay Faults.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1998 — conf
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.
Asian Test Symposium
Irith Pomeranz, W. Kent Fuchs
1998 — conf
A Generalized Test Generation Procedure for Path Delay Faults.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1998 A conf
A Synthesis Procedure for Flexible Logic Functions.
DATE
Irith Pomeranz, Sudhakar M. Reddy
1998 A conf
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Delay fault models for VLSI circuits1.
Integr.
Irith Pomeranz, Sudhakar M. Reddy
1998 A conf
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.
DATE
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Design-for-testability for path delay faults in large combinational circuits using test points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Functional test generation for delay faults in combinational circuits.
ACM Trans. Design Autom. Electr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
1998 C conf
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1998 Misc conf
MIX: A Test Generation System for Synchronous Sequential Circuits.
VLSI Design
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998 Misc conf
On Removing Redundant Faults in Synchronous Sequential Circuits.
VTS
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998 — conf
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits .
Asian Test Symposium
Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
1998 Misc conf
On Synchronizing Sequences and Test Sequence Partitioning.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1998 Misc conf
On Test Compaction Objectives for Combinational and Sequential Circuits.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1998 C conf
On finding undetectable and redundant faults in synchronous sequential circuits.
ICCD
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
On methods to match a test pattern generator to a circuit-under-test.
IEEE Trans. Very Large Scale Integr. Syst.
Irith Pomeranz, Sudhakar M. Reddy
1998 A conf
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.
DATE
Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
1998 — conf
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1998 Misc conf
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Techniques for minimizing power dissipation in scan and combinational circuits during test application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy
1998 — conf
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.
Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
1998 — conf
Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1998 J jnl
Test sequences to achieve high defect coverage for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1997 Misc conf
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.
VLSI Design
Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
1997 — conf
ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1997 A conf
Built-in test generation for synchronous sequential circuits.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1997 J jnl
Compact test sets for high defect coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1997 Misc conf
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1997 A* conf
Fault Simulation under the Multiple Observation Time Approach using Backward Implications.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1997 J jnl
LOCSTEP: a logic-simulation-based test generation procedure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1997 J jnl
On Dictionary-Based Fault Location in Digital Logic Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1997 Misc conf
On Full Reset as a Design-For-Testability Technique.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1997 — conf
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults.
Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy
1997 J jnl
On error correction in macro-based circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1997 — conf
On improving genetic optimization based test generation.
ED&TC
Irith Pomeranz, Sudhakar M. Reddy
1997 Misc conf
On n-detection test sequences for synchronous sequential circuits343.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1997 — conf
On the Compaction of Test Sets Produced by Genetic Optimization.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1997 Misc conf
On the Detection of Reset Faults in Synchronous Sequential Circuits.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1997 — conf
On the use of reset to increase the testability of interconnected finite-state machines.
ED&TC
Irith Pomeranz, Sudhakar M. Reddy
1997 — conf
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1997 J jnl
Test Generation for Multiple State-Table Faults in Finite-State Machines.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1997 C conf
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
1996 — conf
Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1996 C conf
Fault Location Based on Circuit Partitioning.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
1996 A conf
Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.
ITC
Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li
1996 — conf
Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1996 A conf
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1996 — conf
On Double Transition Faults as a Delay Fault Model.
Great Lakes Symposium on VLSI
Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
1996 Misc conf
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1996 A conf
On Potential Fault Detection in Sequential Circuits.
ITC
Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
1996 J jnl
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1996 A* conf
On Static Compaction of Test Sequences for Synchronous Sequential Circuits.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1996 — conf
On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem.
ED&TC
Irith Pomeranz, Sudhakar M. Reddy
1996 — conf
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1996 Misc conf
On minimizing the number of test points needed to achieve complete robust path delay fault testability.
VTS
Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz
1996 J jnl
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1996 Misc conf
On the effects of test compaction on defect coverage.
VTS
Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1996 Misc conf
Synchronization of large sequential circuits by partial reset.
VTS
Yuan Lu, Irith Pomeranz
1995 J jnl
Aliasing Computation Using Fault Simulation with Fault Dropping.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1995 J jnl
An optimal algorithm for cycle breaking in directed graphs.
J. Electron. Test.
Tatiana Orenstein, Zvi Kohavi, Irith Pomeranz
1995 Misc conf
Compact test generation for bridging faults under I
VTS
Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara
1995 J jnl
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1995 A conf
Functional test generation for delay faults in combinational circuits.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1995 J jnl
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1995 — conf
LOCSTEP: A Logic Simulation Based Test Generation Procedure.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1995 A conf
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1995 Misc conf
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.
VLSI Design
Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy
1995 J jnl
NEST: a nonenumerative test generation method for path delay faults in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
1995 J jnl
On Fault Simulation for Synchronous Sequential Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1995 A* conf
On Synthesis-for-Testability of Combinational Logic Circuits.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1995 J jnl
On correction of multiple design errors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1995 — conf
On generating compact test sequences for synchronous sequential circuits.
EURO-DAC
Irith Pomeranz, Sudhakar M. Reddy
1995 — conf
Static compaction for two-pattern test sets.
Asian Test Symposium
Irith Pomeranz, Sudhakar M. Reddy
1995 C conf
Test generation for multiple state-table faults in finite-state machines.
ICCD
Irith Pomeranz, Sudhakar M. Reddy
1994 J jnl
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1994 J jnl
Application of Homing Sequences to Synchronous Sequential Circuit Testing.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1994 A* conf
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1994 A conf
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1994 — conf
On Codeword Testing of Two-Rail and Parity TSC Checkers.
FTCS
Sudhakar M. Reddy, Irith Pomeranz, Rahul Jain
1994 Misc conf
On Determining Symmetries in Inputs of Logic Circuits.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1994 A* conf
On Improving Fault Diagnosis for Synchronous Sequential Circuits.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1994 J jnl
On achieving complete fault coverage for sequential machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1994 Misc conf
On compacting test sets by addition and removal of test vectors.
VTS
Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1994 J jnl
On determining symmetries in inputs of logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1994 A conf
On error correction in macro-based circuits.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1994 Misc conf
On identifying undetectable and redundant faults in synchronous sequential circuits.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1994 A conf
On testing delay faults in macro-based combinational circuits.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1994 J jnl
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1994 J jnl
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1994 — conf
Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times.
FTCS
Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy
1993 J jnl
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Sudhakar M. Reddy
1993 A conf
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1993 — conf
A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis.
EURO-DAC
Irith Pomeranz, Sudhakar M. Reddy
1993 Misc conf
Aliasing computation using fault simulation with fault dropping.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1993 J jnl
COMPACTEST: a method to generate compact test sets for combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1993 J jnl
Classification of Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1993 A* conf
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits.
DAC
Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1993 — conf
Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1993 — conf
EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1993 A conf
Fault dictionary compression and equivalence class computation for sequential circuits.
ICCAD
Paul G. Ryan, W. Kent Fuchs, Irith Pomeranz
1993 — conf
GAFPGA: Genetic algorithm for FPGA technology mapping.
EURO-DAC
Venkataramana Kommu, Irith Pomeranz
1993 A* conf
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits.
DAC
Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
1993 A conf
On diagnosis and correction of design errors.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1993 Misc conf
On the Generation of Weights for Weighted Pseudo Random Testing.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1993 J jnl
STOIC: state assignment based on output/input functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Kwang-Ting Cheng
1993 A conf
Test generation for path delay faults based on learning.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1993 J jnl
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1993 — conf
Theory and Practice of Sequential Machine Testing and Testability.
FTCS
Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
1992 Misc conf
3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set.
VLSI Design
Irith Pomeranz, Sudhakar M. Reddy
1992 — conf
A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1992 J jnl
A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Zvi Kohavi
1992 A conf
An efficient non-enumerative method to estimate path delay fault coverage.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1992 A* conf
At-Speed Delay Testing of Synchronous Sequential Circuits.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1992 A conf
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
ICCAD
Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy
1992 — conf
Effect of Communication in a Parallel Genetic Algorithm.
ICPP (3)
Venkataramana Kommu, Irith Pomeranz
1992 Misc conf
Generalization of independent faults for transition faults.
VTS
Irith Pomeranz, Sudhakar M. Reddy
1992 A conf
On the generation of small dictionaries for fault location.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1992 — conf
SPADES: a simulator for path delay faults in sequential circuits.
EURO-DAC
Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1992 A* conf
State Assignment Using Input/Output Functions.
DAC
Irith Pomeranz, Kwang-Ting Cheng
1992 — conf
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
FTCS
Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller
1992 J jnl
The Multiple Observation Time Test Strategy.
IEEE Trans. Computers
Irith Pomeranz, Sudhakar M. Reddy
1991 A conf
Achieving Complete Delay Fault Testability by Extra Inputs.
ITC
Irith Pomeranz, Sudhakar M. Reddy
1991 A conf
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.
ITC
Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1991 A conf
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy
1991 A* conf
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model.
DAC
Irith Pomeranz, Sudhakar M. Reddy
1991 J jnl
Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion.
IEEE Trans. Computers
Irith Pomeranz, Zvi Kohavi
1991 A conf
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy
1991 — conf
Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times.
FTCS
Irith Pomeranz, Sudhakar M. Reddy
1991 — conf
Testing of Fault-Tolerant Hardware.
Fault-Tolerant Computing Systems
Irith Pomeranz, Sudhakar M. Reddy
1991 J jnl
The minimum test set problem for circuits with nonreconvergent fanout.
J. Electron. Test.
Irith Pomeranz, Zvi Kohavi