Iris Hui-Ru Jiang

129 papers A* 21A 26B 1C 6Journal 34Unranked 39

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Any-Angle Die-to-Die Routing for Advanced Packages with Asymmetric Pin Row Structures, Via Constraints, and Shielding-Aware Reservation. ISPD Hsin-Tzu Chang, Iris Hui-Ru Jiang, Hua-Yu Chang, Chun-Hao Lai
2026	—	`conf`	DCPPC: Digital Computation in Programmable Photonic Circuits. ASP-DAC Jun-Wei Liang, Iris Hui-Ru Jiang, Kai-Hsiang Chiu
2026	J	`jnl`	Introduction to the Special Issue on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. Stephan Held, Gracieli Posser, Iris Hui-Ru Jiang, David G. Chinnery
2026	J	`jnl`	Layout Decomposition and Printing Time Optimization for Inkjet-Printed Electronics. ACM Trans. Design Autom. Electr. Syst. Yi-Ting Lin, Meng Lian, Hu Peng, Bernhard Wolfrum, Tsun-Ming Tseng, Iris Hui-Ru Jiang
2026	J	`jnl`	TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing. ACM Trans. Design Autom. Electr. Syst. Jun-Wei Liang, Iris Hui-Ru Jiang
2026	J	`jnl`	p-Harrow: Optical Logic Synthesis for Efficiency Optimization via Partial Harmonic Mean and Integer Partition. IEEE J. Emerg. Sel. Topics Circuits Syst. Jun-Wei Liang, Iris Hui-Ru Jiang, Kai-Hsiang Chiu, Tung-Yu Su
2025	A*	`conf`	Generative Model Based Standard Cell Timing Library Characterization. DAC Hao-Yu Wu, Hsin-Tzu Chang, Shiuan-Yun Ding, Iris Hui-Ru Jiang, Benson Tsao, Vinson Wu, Wei-Kai Shih
2025	J	`jnl`	Graceful Register Clustering and Rebanking for Power and Timing Balancing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Ting Hsieh, Tung-Wei Lin, Ya-Chu Chang, Hao-Yu Wu, Iris Hui-Ru Jiang
2025	A*	`conf`	Harrow: Synthesis of Optical Logic Circuits via Harmonic Mean and Integer Partition. DAC Jun-Wei Liang, Iris Hui-Ru Jiang, Kai-Hsiang Chiu
2025	J	`jnl`	Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process. ACM Trans. Design Autom. Electr. Syst. Yi-Ting Lin, Kang-Ting Fan, Iris Hui-Ru Jiang
2025	—	`conf`	Multi-Stage CSM Timing Waveform Propagation Accelerated by NLDM Assistance. ISPD Shih-Kai Lee, Pei-Yu Lee, Iris Hui-Ru Jiang
2025	B	`conf`	Passing-Order Decision for Three-to-Two Lane Merging of Connected and Autonomous Vehicles. RTCSA Cheng-Pei Chien, Ben-Hau Chia, Ching-Yun Chang, Shang-Chien Lin, Iris Hui-Ru Jiang, Changliu Liu, Chung-Wei Lin
2024	—	`conf`	Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques. APCCAS Chen-Ho Chen, Chien-Nan Jimmy Liu, Wei-Ting Tu, Tung-Chieh Chen, Iris Hui-Ru Jiang
2024	J	`jnl`	Graph-Based Deadlock Analysis and Prevention for Robust Intelligent Intersection Management. ACM Trans. Cyber Phys. Syst. Kai-En Lin, Kuan-Chun Wang, Yu-Heng Chen, Li-Heng Lin, Ying-Hua Lee, Chung-Wei Lin, Iris Hui-Ru Jiang
2024	A	`conf`	Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. ICCAD Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang
2024	J	`jnl`	Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kevin Kai-Chun Chang, Guan-Ting Liu, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang
2024	—	`conf`	Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack Dependency. ISPD Wei-Chen Tai, Min-Hsien Chung, Iris Hui-Ru Jiang
2024	—	`conf`	Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization. ISPD Chien-Pang Lu, Iris Hui-Ru Jiang, Chung-Ching Peng, Mohd Mawardi Mohd Razha, Alessandro Uber
2024	—	`ed.`	Proceedings of the 2024 International Symposium on Physical Design, ISPD 2024, Taipei, Taiwan, March 12-15, 2024 ISPD Iris Hui-Ru Jiang, Gracieli Posser
2024	—	`conf`	Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops. ISPD Yen-Yu Chen, Hao-Yu Wu, Iris Hui-Ru Jiang, Cheng-Hong Tsai, Chien-Cheng Wu
2023	—	`conf`	EDA for Domain Specific Computing: An Introduction for the Panel. ISPD Iris Hui-Ru Jiang, David G. Chinnery
2023	J	`jnl`	Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig
2023	A*	`conf`	Lightning Talk: All Routes to Timing Closure. DAC Iris Hui-Ru Jiang
2023	—	`ed.`	Proceedings of the 2023 International Symposium on Physical Design, ISPD 2023, Virtual Event, USA, March 26-29, 2023 ISPD David G. Chinnery, Iris Hui-Ru Jiang
2022	—	`conf`	Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines. ISPD Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang
2022	A	`conf`	Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets. DATE Tsung-Lin Tsou, Chung-Wei Lin, Iris Hui-Ru Jiang
2022	C	`conf`	Deadlock Resolution for Intelligent Intersection Management with Changeable Trajectories. IV Li-Heng Lin, Kuan-Chun Wang, Ying-Hua Lee, Kai-En Lin, Chung-Wei Lin, Iris Hui-Ru Jiang
2022	—	`conf`	Intelligent Design Automation for Heterogeneous Integration. ISPD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen
2022	A	`conf`	Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering. DATE Yen-Shuo Chen, Iris Hui-Ru Jiang
2022	A	`conf`	Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning. ICCAD Guan-Ting Liu, Wei-Chen Tai, Yi-Ting Lin, Iris Hui-Ru Jiang, James P. Shiely, Pu-Jen Cheng
2022	A*	`conf`	Timing macro modeling with graph neural networks. DAC Kevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang
2021	A	`conf`	DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo
2021	—	`conf`	Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles. VTC Fall Shang-Chien Lin, Chia-Chu Kung, Lee Lin, Chung-Wei Lin, Iris Hui-Ru Jiang
2021	J	`jnl`	Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Ting Lin, Iris Hui-Ru Jiang
2021	J	`jnl`	OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2021	—	`conf`	Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
2021	A*	`conf`	Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval. DAC Sean Shang-En Tseng, Iris Hui-Ru Jiang, James P. Shiely
2020	C	`conf`	A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles. IV Shang-Chien Lin, Hsiang Hsu, Yi-Ting Lin, Chung-Wei Lin, Iris Hui-Ru Jiang, Changliu Liu
2020	A	`conf`	DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
2020	A	`conf`	Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. ICCAD Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, Cheng-Hong Tsai
2020	—	`conf`	Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. ASP-DAC Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang
2020	A*	`conf`	Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures. DAC Hsien-Han Cheng, Iris Hui-Ru Jiang, Oscar Ou
2020	A	`conf`	Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
2020	A*	`conf`	Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. DAC Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang
2020	A*	`conf`	Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems. DAC Tung-Wei Lin, Wei-Chen Tai, Yu-Cheng Lin, Iris Hui-Ru Jiang
2020	J	`jnl`	iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei-Chun Chang, Iris Hui-Ru Jiang
2019	A	`conf`	DATC RDF-2019: Towards a Complete Academic Reference Design Flow. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
2019	—	`conf`	Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing. ISPD Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam
2019	J	`jnl`	Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles. ACM Trans. Embed. Comput. Syst. Yi-Ting Lin, Hsiang Hsu, Shang-Chien Lin, Chung-Wei Lin, Iris Hui-Ru Jiang, Changliu Liu
2019	—	`conf`	Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement. ISPD Hua-Yu Chang, Iris Hui-Ru Jiang
2019	A*	`conf`	Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. DAC Yi-Ting Lin, Iris Hui-Ru Jiang
2019	—	`conf`	OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2018	A*	`conf`	COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design. DAC Chien-Pang Lu, Iris Hui-Ru Jiang
2018	J	`jnl`	DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. CoRR Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam
2018	A	`conf`	DATC RDF: an academic flow from logic synthesis to detailed routing. ICCAD Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam
2018	—	`conf`	FastPass: Fast timing path search for generalized timing exception handling. ASP-DAC Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen
2018	J	`jnl`	OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
2018	J	`jnl`	OpenMPL: An Open Source Layout Decomposer. CoRR Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2018	—	`conf`	Recent Research and Challenges in Multiple Patterning Layout Decomposition. ISVLSI Iris Hui-Ru Jiang, Hua-Yu Chang
2018	—	`conf`	Timing Macro Modeling for Efficient Hierarchical Timing Analysis. ISVLSI Iris Hui-Ru Jiang, Pei-Yu Lee
2018	J	`jnl`	iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis. ACM Trans. Design Autom. Electr. Syst. Pei-Yu Lee, Iris Hui-Ru Jiang
2017	A	`conf`	DATC RDF: Robust design flow database: Invited paper. ICCAD Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam
2017	A	`conf`	Fast low power rule checking for multiple power domain design. DATE Chien-Pang Lu, Iris Hui-Ru Jiang
2017	J	`jnl`	Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iris Hui-Ru Jiang, Hua-Yu Chang
2017	A*	`conf`	Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation. DAC Wei-Lun Chiu, Iris Hui-Ru Jiang, Chien-Pang Lu, Yu-Tung Chang
2017	A*	`conf`	iClaire: A Fast and General Layout Pattern Classification Algorithm. DAC Wei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu
2017	—	`conf`	iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis. ISPD Pei-Yu Lee, Iris Hui-Ru Jiang, Ting-You Yang
2016	J	`jnl`	Analytical Clustering Score with Application to Postplacement Register Clustering. ACM Trans. Design Autom. Electr. Syst. Chang Xu, Guojie Luo, Peixin Li, Yiyu Shi, Iris Hui-Ru Jiang
2016	A*	`conf`	Multiple patterning layout decomposition considering complex coloring rules. DAC Hua-Yu Chang, Iris Hui-Ru Jiang
2016	A	`conf`	OWARU: free space-aware timing-driven incremental placement. ICCAD Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
2016	A	`conf`	OpenDesign flow database: the infrastructure for VLSI design and design automation research. ICCAD Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li
2016	—	`conf`	Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li
2016	A	`conf`	Resource-aware functional ECO patch generation. DATE An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou
2015	—	`conf`	Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging. ISPD Chang Xu, Peixin Li, Guojie Luo, Yiyu Shi, Iris Hui-Ru Jiang
2015	A*	`conf`	Criticality-dependency-aware timing characterization and analysis. DAC Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang
2015	J	`jnl`	Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam
2015	A	`conf`	GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design. ICCAD Chien-Pang Lu, Iris Hui-Ru Jiang, Chin-Hsiung Hsu
2015	J	`jnl`	Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang
2015	A	`conf`	iTimerC 2.0: Fast Incremental Timing and CPPR Analysis. ICCAD Pei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, Yu-Ming Yang
2014	A	`conf`	DRC-based hotspot detection considering edge tolerance and incomplete specification. ICCAD Yen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, Charles C. Chiang
2014	J	`jnl`	Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. ACM Trans. Design Autom. Electr. Syst. An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou
2014	A*	`conf`	Functional ECO Using Metal-Configurable Gate-Array Spare Cells. DAC Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2014	J	`jnl`	PushPull: Short-Path Padding for Timing Error Resilient Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho
2014	A	`conf`	Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. ICCAD Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes
2014	A	`conf`	The overview of 2014 CAD contest at ICCAD. ICCAD Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li
2014	A	`conf`	iTimerC: common path pessimism removal using effective reduction methods. ICCAD Yu-Ming Yang, Yu-Wei Chang, Iris Hui-Ru Jiang
2013	J	`jnl`	ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2013	—	`conf`	FF-bond: multi-bit flip-flop bonding at placement. ISPD Chang-Cheng Tsai, Yiyu Shi, Guojie Luo, Iris Hui-Ru Jiang
2013	A*	`conf`	Machine-learning-based hotspot detection using topological classification and critical feature extraction. DAC Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang
2013	J	`jnl`	Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Long Chang, Iris Hui-Ru Jiang
2013	—	`conf`	PushPull: short path padding for timing error resilient circuits. ISPD Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho
2013	A	`conf`	The overview of 2013 CAD contest at ICCAD. ICCAD Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan
2012	A*	`conf`	Accurate process-hotspot detection using critical design rule extraction. DAC Yen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, Charles C. Chiang
2012	J	`jnl`	ECOS: Stable Matching Based Metal-Only ECO Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Iris Hui-Ru Jiang, Hua-Yu Chang
2012	J	`jnl`	Generic Integer Linear Programming Formulation for 3D IC Partitioning. J. Inf. Sci. Eng. Wan-Yu Lee, Iris Hui-Ru Jiang, Tsung-Wan Mei
2012	J	`jnl`	INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang
2012	—	`conf`	Novel pulsed-latch replacement based on time borrowing and spiral clustering. ISPD Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen
2012	A	`conf`	Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. ICCAD Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li
2012	J	`jnl`	Reliability-Driven Power/Ground Routing for Analog ICs. ACM Trans. Design Autom. Electr. Syst. Jing-Wei Lin, Tsung-Yi Ho, Iris Hui-Ru Jiang
2012	J	`jnl`	Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012	A*	`conf`	Timing ECO optimization using metal-configurable gate-array spare cells. DAC Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2012	J	`jnl`	WiT: Optimal Wiring Topology for Electromigration Avoidance. IEEE Trans. Very Large Scale Integr. Syst. Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang
2011	—	`conf`	3DICE: 3D IC cost evaluation based on fast tier number estimation. ISQED Cheng-Chi Chan, Yen-Ting Yu, Iris Hui-Ru Jiang
2011	—	`conf`	INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. ISPD Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen
2011	A*	`conf`	Simultaneous functional and timing ECO. DAC Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2011	A	`conf`	Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
2010	—	`conf`	Analog placement and global routing considering wiring symmetry. ISQED Yu-Ming Yang, Iris Hui-Ru Jiang
2010	C	`conf`	Live Demo: ECOS 1.0: A metal-only ECO synthesizer. ISCAS Iris Hui-Ru Jiang, Hua-Yu Chang
2010	—	`conf`	Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. ISPD Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang
2010	—	`conf`	Simultaneous voltage island generation and floorplanning. SoCC Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen
2009	—	`conf`	Generic integer linear programming formulation for 3D IC partitioning. SoCC Iris Hui-Ru Jiang
2009	A*	`conf`	Matching-based minimum-cost spare cell selection for design changes. DAC Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung
2009	C	`conf`	POSA: Power-state-aware Buffered Tree Construction. ISCAS Iris Hui-Ru Jiang, Ming-Hua Wu
2009	—	`conf`	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. ACM Great Lakes Symposium on VLSI Wan-Yu Lee, Iris Hui-Ru Jiang
2008	C	`conf`	Configurable rectilinear Steiner tree construction for SoC and nano technologies. ICCD Iris Hui-Ru Jiang, Yen-Ting Yu
2008	C	`conf`	Power-state-aware buffered tree construction. ICCD Iris Hui-Ru Jiang, Ming-Hua Wu
2008	—	`conf`	Unification of obstacle-avoiding rectilinear Steiner tree construction. SoCC Iris Hui-Ru Jiang, Shung-Wei Lin, Yen-Ting Yu
2006	—	`conf`	Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. SoCC Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang
2006	J	`jnl`	Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
2004	J	`jnl`	Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2003	—	`conf`	Simultaneous floorplanning and buffer block planning. ASP-DAC Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2002	—	`conf`	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ISQED Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang
2001	—	`conf`	On placement and routing of wafer scale memory. ICECS Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, Tai-Sheng Feng
2000	J	`jnl`	Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
2000	—	`conf`	Optimal reliable crosstalk-driven interconnect optimization. ISPD Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
1999	A	`conf`	A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
1999	—	`conf`	Hierarchical Floorplan Design on the Internet. ASP-DAC Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang
1999	A*	`conf`	Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
1999	A	`conf`	Optimum loading dispersion for high-speed tree-type decision circuitry. ICCAD Jie-Hong Roland Jiang, Iris Hui-Ru Jiang