Ireneusz Brzozowski

18 papers C 2Journal 6Unranked 10
YearRankTypeTitle / Venue / Authors
2026 J jnl
Non-uniform spiking touch sensor for classification of movement patterns using neural networks.
Expert Syst. Appl.
Michal Markiewicz, Szymon Janusz, Ireneusz Brzozowski
2025 — conf
CMOS OTA for Detector Readout Electronics Integrator in the ALICE FIT Project.
MIXDES
Jakub Miszczynski, Piotr Otfinowski, Andrzej Laczewski, Michal Grzegorzek, Ireneusz Brzozowski, Cezary Worek, Piotr Wiacek, Pawel Russek, Jacek Kitowski, Jacek Otwinowski
2024 J jnl
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder.
ACM Trans. Design Autom. Electr. Syst.
Ireneusz Brzozowski
2024 J jnl
Spiking Neural Network Pressure Sensor.
Neural Comput.
Michal Markiewicz, Ireneusz Brzozowski, Szymon Janusz
2021 J jnl
Multi-state MRAM cells for hardware neuromorphic computing.
CoRR
Piotr Rzeszut, Jakub Checinski, Ireneusz Brzozowski, Slawomir Zietek, Witold Skowronski, Tomasz Stobiecki
2021 — conf
Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders.
MIXDES
Ireneusz Brzozowski
2020 — conf
Comparative Analysis of Power Consumption of Parallel Prefix Adders.
MIXDES
Ireneusz Brzozowski
2016 — conf
Extraction of temperature dependent parameters for an electrothermal model of thermoelectric energy harvester.
MIXDES
Piotr Dziurdzia, Piotr Bratek, Ireneusz Brzozowski, Wojciech Gelmuda, Jacek Ostrowski, Andrzej Kos
2014 J jnl
Designing of low-power data oriented adders.
Microelectron. J.
Ireneusz Brzozowski, Andrzej Kos
2014 — conf
Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm.
MIXDES
Jacek Jasielski, Stanislaw W. Kuta, Witold Machowski, Ireneusz Brzozowski, Wojciech Kolodziejski
2013 — conf
An analysis of full adder cells for low-power data oriented adders design.
MIXDES
Ireneusz Brzozowski, Damian Palys, Andrzej Kos
2013 — conf
Universal design method of n-to-2n decoders.
MIXDES
Ireneusz Brzozowski, Lukasz Zachara, Andrzej Kos
2008 J jnl
A new approach to power estimation and reduction in CMOS digital circuits.
Integr.
Ireneusz Brzozowski, Andrzej Kos
2007 C conf
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.
DDECS
Ireneusz Brzozowski, Andrzej Kos
2005 — conf
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.
PATMOS
Ireneusz Brzozowski, Andrzej Kos
2001 C conf
Practical Aspects of Logic Synthesis Based on Functional Decomposition.
DSD
Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski
2000 — conf
Energy consumption minimisation with new synthesis method.
ICECS
Ireneusz Brzozowski, Andrzej Kos
1999 — conf
Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity.
EUROMICRO
Ireneusz Brzozowski, Andrzej Kos