Ippei Akita

26 papers C 2Journal 15Unranked 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System.
IEEE J. Solid State Circuits
Hiroshi Fuketa, Ippei Akita, Hanpei Koike, Takahiro Mori
2025 J jnl
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Ippei Akita, Kousuke Miyaji, Seung-Tak Ryu, Masoud Babaie, Negar Reiskarimian
2024 — conf
3.5 A 4mW 45pT/√Hz Magnetoimpedance-Based ΔΣ Magnetometer with Background Gain Calibration and Short-Time CDS Techniques.
ISSCC
Ippei Akita, Shunichi Tatematsu
2023 J jnl
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
2022 — conf
A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement.
ISSCC
Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki
2022 — conf
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution.
VLSI Technology and Circuits
Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori
2022 J jnl
An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer.
IEEE J. Solid State Circuits
Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki
2020 J jnl
A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications.
IEEE J. Solid State Circuits
Ippei Akita, Takayuki Okazawa, Yoshihiko Kurui, Akira Fujimoto, Takashi Asano
2019 J jnl
A 0.338 cm
IEEE Trans. Biomed. Circuits Syst.
Dejan Rozgic, Vahagn Hokhikyan, Wenlong Jiang, Ippei Akita, Sina Basir-Kazeruni, Hariprasad Chandrakumar, Dejan Markovic
2019 — conf
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.
A-SSCC
Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
2018 — conf
A 181NW 970µG✓HZ Accelerometer Analog Front-End Employing Feedforward Noise Reduction Technique.
VLSI Circuits
Ippei Akita, Takayuki Okazawa, Yoshihiko Kurui, Akira Fujimoto, Takashi Asano
2018 J jnl
A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique.
IEICE Trans. Electron.
Takayuki Okazawa, Ippei Akita
2018 J jnl
A Time-Domain Analog Spatial Compressed Sensing Encoder for Multi-Channel Neural Recording.
Sensors
Takayuki Okazawa, Ippei Akita
2017 — conf
A robust and low-power synchronization technique of coarse-and-fine conversion parts in ring-oscillator-based time-to-digital converters.
ICECS
Takayuki Okazawa, Ippei Akita
2015 J jnl
A current noise reduction technique in chopper instrumentation amplifier for high-impedance sensors.
IEICE Electron. Express
Ippei Akita, Makoto Ishida
2015 J jnl
Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.
Sensors
Kenji Okabe, Horagodage Prabhath Jeewan, Shota Yamagiwa, Takeshi Kawano, Makoto Ishida, Ippei Akita
2013 — conf
A 0.06mm
ISSCC
Ippei Akita, Makoto Ishida
2013 J jnl
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura
2011 — conf
A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS.
ESSCIRC
Ippei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata
2011 — conf
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier.
A-SSCC
Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura
2011 J jnl
Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch.
IEEE Trans. Circuits Syst. II Express Briefs
Ippei Akita, Tetsuro Itakura, Kei Shiraishi
2009 J jnl
A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-µm CMOS.
IEEE J. Solid State Circuits
Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
2008 J jnl
A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-µm CMOS.
IEICE Trans. Electron.
Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
2007 C conf
Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter.
ISCAS
Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
2007 J jnl
Synthesis Method of All Low-Voltage CMOS Instantaneous-Companding Log Domain Integrators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
2006 C conf
Low-voltage CMOS syllabic-companding log domain filter.
ISCAS
Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro