Ioannis Savidis

96 papers A* 2A 3C 29Misc 1Journal 26Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	DNA: DC Nodal Analysis Attack for Evaluation of Analog Obfuscation Techniques. ACM Trans. Design Autom. Electr. Syst. Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
2025	—	`conf`	Avoiding Malicious Nodes of a 3-D NoC with Security-Aware Priority-Based Routing. ACM Great Lakes Symposium on VLSI Alec Aversa, Hasin Ishraq Reefat, Naghmeh Karimi, Ioannis Savidis
2025	J	`jnl`	Deep Representation Learning for Electronic Design Automation. CoRR Pratik Shrestha, Saran Phatharodom, Alec Aversa, David Blankenship, Zhengfeng Wu, Ioannis Savidis
2025	C	`conf`	Differentiable Graph Neural Networks for Wirelength Estimation. ISCAS Zhengfeng Wu, Pratik Shrestha, Saran Phatharodom, Ioannis Savidis
2025	J	`jnl`	Emerging ML-AI Techniques for Analog and RF EDA. CoRR Zhengfeng Wu, Ziyi Chen, Nnaemeka Achebe, Vaibhav Venugopal Rao, Pratik Shrestha, Ioannis Savidis
2025	C	`conf`	Representation Learning for Digital Integrated Circuit Design Automation. ICCD Pratik Shrestha, Ioannis Savidis
2025	J	`jnl`	Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array. IEEE Trans. Very Large Scale Integr. Syst. Ziyi Chen, Ioannis Savidis
2025	A	`conf`	TARN: Trust Aware Routing to Enhance Security in 3D Network-on-Chips. DATE Hasin Ishraq Reefat, Alec Aversa, Ioannis Savidis, Naghmeh Karimi
2024	C	`conf`	Block Configuration Algorithms for a Reconfigurable Analog Array. ISCAS Ziyi Chen, Ioannis Savidis
2024	—	`conf`	Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling. ISQED Zhengfeng Wu, Ioannis Savidis
2024	C	`conf`	DNA: DC Nodal Analysis Attack for Analog Circuits. ISCAS Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
2024	—	`conf`	EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation. ISQED Pratik Shrestha, Ioannis Savidis
2024	—	`conf`	EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation. ACM Great Lakes Symposium on VLSI Pratik Shrestha, Alec Aversa, Saran Phatharodom, Ioannis Savidis
2024	C	`conf`	Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits. ISCAS Zhengfeng Wu, Ioannis Savidis
2024	—	`conf`	Harnessing Heterogeneity for Targeted Attacks on 3-D ICs. ACM Great Lakes Symposium on VLSI Alec Aversa, Ioannis Savidis
2023	C	`conf`	A Power Side-Channel Attack on Flash ADC. ISCAS Ziyi Chen, Ioannis Savidis
2023	C	`conf`	Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies. ISCAS Zhengfeng Wu, Ioannis Savidis
2023	C	`conf`	Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect. ISCAS Pratik Shrestha, Ioannis Savidis
2023	J	`jnl`	Hidden Costs of Analog Deobfuscation Attacks. IEEE Trans. Very Large Scale Integr. Syst. Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
2023	—	`conf`	Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation. MLCAD Zhengfeng Wu, Isabel Song, Ioannis Savidis
2022	—	`conf`	Adaptive-Gravity: A Defense Against Adversarial Samples. ISQED Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan
2022	J	`jnl`	Adaptive-Gravity: A Defense Against Adversarial Samples. CoRR Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan
2022	—	`conf`	Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits. ISQED Vaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis
2022	—	`ed.`	GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022 ACM Great Lakes Symposium on VLSI Ioannis Savidis, Avesta Sasan, Himanshu Thapliyal, Ronald F. DeMara
2022	—	`conf`	Graph Representation Learning for Gate Arrival Time Prediction. MLCAD Pratik Shrestha, Saran Phatharodom, Ioannis Savidis
2022	—	`conf`	Practical Performance of Analog Attack Techniques. HOST Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
2022	—	`conf`	RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis. ACM Great Lakes Symposium on VLSI Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Sayed Aresh Beheshti-Shirazi, Ali Mirzaeian, Xiaojie Guo, Sai Manoj P. D., Houman Homayoun, Ioannis Savidis, Liang Zhao, Avesta Sasan
2022	C	`conf`	Reconfigurable Analog Array for Hardware Security. ISCAS Ziyi Chen, Ioannis Savidis
2022	C	`conf`	Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking. ISCAS Pratik Shrestha, Ioannis Savidis
2022	C	`conf`	Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes. ISCAS Zhengfeng Wu, Ioannis Savidis
2022	—	`conf`	Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks. MLCAD Zhengfeng Wu, Ioannis Savidis
2021	—	`conf`	A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop. ACM Great Lakes Symposium on VLSI Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj P. D., Ioannis Savidis, Houman Homayoun, Avesta Sasan
2021	—	`conf`	Energy Efficient Computing with Heterogeneous DNN Accelerators. AICAS Md Shazzad Hossain, Ioannis Savidis
2021	—	`ed.`	GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021. ACM Great Lakes Symposium on VLSI Yiran Chen, Victor V. Zhirnov, Avesta Sasan, Ioannis Savidis
2021	J	`jnl`	Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyle Juretus, Ioannis Savidis
2021	J	`jnl`	Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Md Shazzad Hossain, Ioannis Savidis
2021	J	`jnl`	Performance and Security Analysis of Parameter-Obfuscated Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. Vaibhav Venugopal Rao, Ioannis Savidis
2021	C	`conf`	Reconfigurable Array for Analog Applications. ICCD Ziyi Chen, Ioannis Savidis
2021	—	`conf`	SAT-attack Resilience Measure for Access Restricted Circuits. ACM Great Lakes Symposium on VLSI Saran Phatharodom, Avesta Sasan, Ioannis Savidis
2021	J	`jnl`	Synthesis of Hidden State Transitions for Sequential Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyle Juretus, Ioannis Savidis
2021	—	`conf`	Variation-aware Analog Circuit Sizing with Classifier Chains. MLCAD Zhengfeng Wu, Ioannis Savidis
2020	—	`conf`	CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing. MLCAD Zhengfeng Wu, Ioannis Savidis
2020	J	`jnl`	Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyle Juretus, Ioannis Savidis
2020	J	`jnl`	Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing. Microelectron. J. Md Shazzad Hossain, Ioannis Savidis
2020	A	`conf`	Dynamic idle core management and leakage current reuse in MPSoC platforms. ISLPED Md Shazzad Hossain, Ioannis Savidis
2020	C	`conf`	Modeling SAT-Attack Search Complexity. ISCAS Saran Phatharodom, Nagarajan Kandasamy, Ioannis Savidis
2020	J	`jnl`	Physical Layer Encryption for Wireless OFDM Communication Systems. J. Hardw. Syst. Secur. Marko Jacovic, Kyle Juretus, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
2020	J	`jnl`	Recycling of unused leakage current for energy efficient multi-voltage systems. Microelectron. J. Md Shazzad Hossain, Ioannis Savidis
2020	C	`conf`	Reducing Logic Locking Key Leakage through the Scan Chain. ISCAS Kyle Juretus, Ioannis Savidis
2020	C	`conf`	Security Vulnerabilities of Obfuscated Analog Circuits. ISCAS Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
2019	C	`conf`	Applying Swarm Intelligence to Distributed On-Chip Power Management. ICCD Divya Pathak, Ioannis Savidis
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	C	`conf`	Increasing the SAT Attack Resiliency of In-Cone Logic Locking. ISCAS Kyle Juretus, Ioannis Savidis
2019	C	`conf`	Mesh Based Obfuscation of Analog Circuit Properties. ISCAS Vaibhav Venugopal Rao, Ioannis Savidis
2019	C	`conf`	Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems. ISCAS Md Shazzad Hossain, Ioannis Savidis
2019	A	`conf`	Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
2019	—	`conf`	Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. ACM Great Lakes Symposium on VLSI Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis
2019	J	`jnl`	Securing Wireless Communication via Hardware-Based Packet Obfuscation. J. Hardw. Syst. Secur. James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
2018	J	`jnl`	ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun
2018	—	`conf`	Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. APCCAS Kyle Juretus, Ioannis Savidis
2018	C	`conf`	Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. ICCD David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead
2018	—	`conf`	Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery. IGSC Md Shazzad Hossain, Ioannis Savidis
2018	C	`conf`	Noise Constrained Optimum Selection of Supply Voltage for IoT Applications. ISCAS Md Shazzad Hossain, Ioannis Savidis
2018	J	`jnl`	On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors. IEEE Trans. Very Large Scale Integr. Syst. Divya Pathak, Ioannis Savidis
2018	—	`conf`	Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning. ASP-DAC Hossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun
2018	—	`conf`	Securing the Systems of the Future - Techniques for a Shifting Attack Space. ACM Great Lakes Symposium on VLSI Ioannis Savidis, Swarup Bhunia, Gang Qu, Matthew J. Casto, Jeremy Muldavin
2018	C	`conf`	Time Domain Sequential Locking for Increased Security. ISCAS Kyle Juretus, Ioannis Savidis
2018	—	`conf`	Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory. APCCAS Vaibhav Venugopal Rao, Ioannis Savidis
2017	—	`conf`	Bi-directional input/output circuits with integrated level shifters for near-threshold computing. MWSCAS Md Shazzad Hossain, Ioannis Savidis
2017	—	`conf`	Clock tree synthesis for heterogeneous 3-D integrated circuits. SLIP Isuru Daulagala, Ioannis Savidis
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	—	`conf`	Parameter biasing obfuscation for analog IP protection. HOST Vaibhav Venugopal Rao, Ioannis Savidis
2017	Misc	`conf`	Physical gate based preamble obfuscation for securing wireless communication. ICNC James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
2017	—	`conf`	Protecting analog circuits with parameter biasing obfuscation. LATS Vaibhav Venugopal Rao, Ioannis Savidis
2017	J	`jnl`	Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery. IEEE Trans. Very Large Scale Integr. Syst. Divya Pathak, Houman Homayoun, Ioannis Savidis
2017	—	`conf`	Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery. ACM Great Lakes Symposium on VLSI Divya Pathak, Houman Homayoun, Ioannis Savidis
2016	—	`conf`	A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures. SAMOS Kostas Siozios, Ioannis Savidis, Dimitrios Soudris
2016	C	`conf`	Energy efficient on-chip power delivery with run-time voltage regulator clustering. ISCAS Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis
2016	J	`jnl`	Heterogeneous 3-D circuits: Integrating free-space optics with CMOS. Microelectron. J. Ioannis Savidis, Berkehan Ciftcioglu, Jie Xu, Jianyun Hu, Manish Jain, Rebecca Berman, Jing Xue, Peng Liu, Duncan Moore, Gary Wicks, Michael C. Huang, Hui Wu, Eby G. Friedman
2016	—	`conf`	Load Balanced On-Chip Power Delivery for Average Current Demand. ACM Great Lakes Symposium on VLSI Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis
2016	—	`conf`	Reduced Overhead Gate Level Logic Encryption. ACM Great Lakes Symposium on VLSI Kyle Juretus, Ioannis Savidis
2016	C	`conf`	Reducing logic encryption overhead through gate level key insertion. ISCAS Kyle Juretus, Ioannis Savidis
2016	C	`conf`	Robust near-threshold inverter with improved performance for ultra-low power applications. ISCAS Md Shazzad Hossain, Ioannis Savidis
2015	A*	`conf`	ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling. DAC Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun
2015	J	`jnl`	Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Ioannis Savidis, Boris Vaisband, Eby G. Friedman
2015	C	`conf`	Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping. ICCD Mohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis, Houman Homayoun
2014	—	`conf`	Run-time voltage detection circuit for 3-D IC power delivery. SoCC Divya Pathak, Ioannis Savidis
2014	C	`conf`	Thermal conduction path analysis in 3-D ICs. ISCAS Boris Vaisband, Ioannis Savidis, Eby G. Friedman
2013	J	`jnl`	Power Noise in TSV-Based 3-D Integrated Circuits. IEEE J. Solid State Circuits Ioannis Savidis, Selçuk Köse, Eby G. Friedman
2011	J	`jnl`	Clock Distribution Networks in 3-D Integrated Systems. IEEE Trans. Very Large Scale Integr. Syst. Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman
2011	C	`conf`	Clock distribution models of 3-D integrated systems. ISCAS Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman
2011	J	`jnl`	Thermal analysis of oxide-confined VCSEL arrays. Microelectron. J. Jinhui Wang, Ioannis Savidis, Eby G. Friedman
2010	A*	`conf`	An intra-chip free-space optical interconnect. ISCA Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore
2010	J	`jnl`	Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectron. J. Ioannis Savidis, Syed M. Alam, Ankur Jain, Scott Pozder, Robert E. Jones, Ritwik Chatterjee
2008	—	`conf`	Clock distribution networks for 3-D ictegrated Circuits. CICC Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman
2008	C	`conf`	Electrical modeling and characterization of 3-D vias. ISCAS Ioannis Savidis, Eby G. Friedman