Insup Shin - RankMe

15 papers A* 2A 2Journal 7Unranked 4

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
2015	J	`jnl`	Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Insup Shin, Jae-Joon Kim, Youngsoo Shin
2014	J	`jnl`	HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik
2014	—	`conf`	Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC Insup Shin, Jae-Joon Kim, Youngsoo Shin
2013	A	`conf`	A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
2013	J	`jnl`	Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. J. Circuits Syst. Comput. Donkyu Baek, Insup Shin, Youngsoo Shin
2012	—	`conf`	Gate delay modeling for static timing analysis of body-biased circuits. ICICDT Donkyu Baek, Insup Shin, Youngsoo Shin
2012	J	`jnl`	HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin
2012	—	`conf`	Introducing irregularity to routing architecture of structured ASIC for better routability. FPT Insup Shin, Donkyu Baek, Youngsoo Shin
2012	J	`jnl`	Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Seomun, Insup Shin, Youngsoo Shin
2011	—	`conf`	Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin
2010	J	`jnl`	HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin
2010	A*	`conf`	Synthesis and implementation of active mode power gating circuits. DAC Jun Seomun, Insup Shin, Youngsoo Shin
2009	A	`conf`	HLS-l: High-level synthesis of high performance latch-based circuits. DATE Seungwhun Paik, Insup Shin, Youngsoo Shin
2009	A*	`conf`	Register allocation for high-level synthesis using dual supply voltages. DAC Insup Shin, Seungwhun Paik, Youngsoo Shin