Inhak Han

11 papers A* 1A 1C 1Journal 3Unranked 5
YearRankTypeTitle / Venue / Authors
2019 A conf
Clock Gating Synthesis of Netlist with Cyclic Logic Paths.
ICCAD
Yonghwi Kwon, Inhak Han, Youngsoo Shin
2018 J jnl
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops.
ACM Trans. Design Autom. Electr. Syst.
Inhak Han, Youngsoo Shin
2018 C conf
Transient Clock Power Estimation of Pre-CTS Netlist.
ISCAS
Yonghwi Kwon, Jinwook Jung, Inhak Han, Youngsoo Shin
2016 — conf
Buffer insertion to remove hold violations at multiple process corners.
ASP-DAC
Inhak Han, Daijoon Hyun, Youngsoo Shin
2016 — conf
Register grouping for synthesis of clock gating logic.
ICICDT
Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin
2014 J jnl
Simplifying Clock Gating Logic by Matching Factored Forms.
IEEE Trans. Very Large Scale Integr. Syst.
Inhak Han, Youngsoo Shin
2013 — conf
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops.
ICICDT
Inhak Han, Youngsoo Shin
2012 J jnl
Clock Gating Synthesis of Pulsed-Latch Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin
2012 — conf
Synthesis of clock gating logic through factored form matching.
ICICDT
Inhak Han, Youngsoo Shin
2011 — conf
Pulser gating: A clock gating of pulsed-latch circuits.
ASP-DAC
Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin
2011 A* conf
Thermal signature: a simple yet accurate thermal index for floorplan optimization.
DAC
Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin
2025 Best paper conf
Assessing the Effectiveness of the Tigress Obfuscator Against MOPSA and BinaryNinja.
CheckMATE
Nicolò Altamura, Enrico Bragastini, Marco Campion, Mila Dalla Preda
2026 Best paper preprint
ASSEMBLAGE-DEEPHISTORY: A Cross-Build Binary Dataset with Temporal Coverage.
arXiv
Chang Liu, Noah Fleischmann, Nicolò Altamura, Edward Raff, James Holt, Kristopher Micinski