| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | J | jnl |
Neuroinformatics
|
| 2025 | B | conf |
ISPASS
|
| 2025 | J | jnl |
IEEE Trans. Emerg. Top. Comput.
|
| 2024 | J | jnl |
CoRR
|
| 2023 | — | conf |
CICC
|
| 2023 | J | jnl |
ACM Comput. Surv.
|
| 2023 | J | jnl |
CoRR
|
| 2022 | A | conf |
ICCAD
|
| 2022 | A | conf |
DATE
|
| 2022 | A* | conf |
DAC
|
| 2022 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2022 | A | conf |
DATE
|
| 2021 | A | conf |
DATE
|
| 2021 | A | conf |
ICCAD
|
| 2021 | A | conf |
ICDCS
|
| 2021 | J | jnl |
CoRR
|
| 2021 | — | conf |
AICAS
|
| 2021 | J | jnl |
CoRR
|
| 2021 | A* | conf |
DAC
|
| 2021 | J | jnl |
CoRR
|
| 2020 | J | jnl |
IEEE Micro
|
| 2020 | J | jnl |
CoRR
|
| 2020 | J | jnl |
Nat. Mach. Intell.
|
| 2020 | A* | conf |
DAC
|
| 2020 | J | jnl |
CoRR
|
| 2020 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2020 | J | jnl |
CoRR
|
| 2020 | A* | conf |
DAC
|
| 2020 | J | jnl |
Proc. IEEE
|
| 2020 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2020 | J | jnl |
CoRR
|
| 2019 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2019 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2019 | J | jnl |
IEEE Access
|
| 2019 | J | jnl |
CoRR
|
| 2019 | J | jnl |
CoRR
|
| 2019 | J | jnl |
IBM J. Res. Dev.
|
| 2019 | B | conf |
IJCNN
|
| 2019 | J | jnl |
CoRR
|
| 2019 | C | conf |
ICCC
|
| 2019 | J | jnl |
Games Econ. Behav.
|
| 2018 | J | jnl |
CoRR
|
| 2018 | J | jnl |
CoRR
|
| 2018 | J | jnl |
CoRR
|
| 2018 | J | jnl |
CoRR
|
| 2018 | J | jnl |
CoRR
|
| 2018 | J | jnl |
IEEE Trans. Emerg. Top. Comput. Intell.
|
| 2017 | J | jnl |
CoRR
|
| 2017 | J | jnl |
CoRR
|
| 2015 | — | conf |
A selectorless RRAM with record memory window and nonlinearity based on trap filled limit mechanism.
NVMTS
|
| 2008 | J | jnl |
Decis. Support Syst.
|
| 2006 | J | jnl |
Games Econ. Behav.
|
| 2005 | — | conf |
PACIS
|