Indradeep Ghosh

55 papers A* 6A 5B 3C 3Misc 6Journal 17Unranked 14
YearRankTypeTitle / Venue / Authors
2022 conf
ICCS (3)
Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2022 J jnl
CoRR
Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2022 Misc conf
SEC
Hanjing Xu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh
2022 conf
ICDM (Workshops)
Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2022 J jnl
CoRR
Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2021 B conf
IDA
Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh
2020 J jnl
CoRR
Osman Asif Malik, Hayato Ushijima-Mwesigwa, Arnab Roy, Avradip Mandal, Indradeep Ghosh
2020 J jnl
CoRR
Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh
2017 J jnl
IEEE Softw.
Hiroaki Yoshida, Guodong Li, Takuki Kamiya, Indradeep Ghosh, Sreeranga P. Rajan, Susumu Tokumoto, Kazuki Munakata, Tadahiro Uehara
2016 conf
SIGSOFT FSE
Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara
2016 A conf
ISSTA
Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara
2015 A conf
ICST
Cuong Nguyen, Hiroaki Yoshida, Mukul R. Prasad, Indradeep Ghosh, Koushik Sen
2014 conf
SIGSOFT FSE
Guodong Li, Esben Andreasen, Indradeep Ghosh
2013 A* conf
ICSE
Indradeep Ghosh, Nastaran Shafiei, Guodong Li, Wei-Fan Chiang
2013 conf
Haifa Verification Conference
Guodong Li, Indradeep Ghosh
2013 conf
Haifa Verification Conference
Guodong Li, Indradeep Ghosh
2012 B conf
PPoPP
Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan
2011 A* conf
CAV
Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan
2009 conf
ICSE Companion
Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara
2008 B conf
APLAS
Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid
2008 book
Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad
2006 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
2006 conf
ISQED
Indradeep Ghosh, Mukul R. Prasad
2005 conf
Asian Test Symposium
Indradeep Ghosh
2004 Misc conf
VLSI Design
Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita
2003 conf
Asian Test Symposium
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
2003 A conf
ITC
Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
2003 conf
ASP-DAC
Farzan Fallah, Indradeep Ghosh, Masahiro Fujita
2003 conf
ACM Great Lakes Symposium on VLSI
Indradeep Ghosh, Srivaths Ravi
2003 C conf
ICCD
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
2002 conf
ASP-DAC/VLSI Design
Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
2001 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Masahiro Fujita
2001 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
2001 conf
HLDVT
Farzan Fallah, Indradeep Ghosh
2000 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
2000 C conf
ICCD
Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
2000 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
2000 A* conf
DAC
Indradeep Ghosh, Masahiro Fujita
2000 Misc conf
VLSI Design
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
1999 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1999 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1998 A* conf
DAC
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
1998 A* conf
DAC
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
1998 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1998 J jnl
J. Electron. Test.
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998 Misc conf
VLSI Design
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998 J jnl
Integr.
Indradeep Ghosh, Niraj K. Jha
1997 A conf
ITC
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1997 Misc conf
VLSI Design
Sudipta Bhawmik, Indradeep Ghosh
1997 J jnl
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1997 A* conf
DAC
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1996 A conf
ICCAD
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1995 C conf
ICCD
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1995 J jnl
Int. J. Pattern Recognit. Artif. Intell.
Indradeep Ghosh, Bandana Majumdar
1994 Misc conf
VLSI Design
Indradeep Ghosh, Bandana Majumdar
redb/extractors/decompiler/bninja/arch/x86.py
← Index redb/extractors/decompiler/bninja/arch/x86.py python
from binaryninja.enums import (
    InstructionTextTokenType,
)

# Support both package and standalone imports
try:
    from .architecture import Architecture
except ImportError:
    # Fallback to absolute imports (for multiprocessing spawned processes)
    from redb.extractors.decompiler.bninja.arch.architecture import Architecture


class Arch_x86(Architecture):
    """The concrete class for architecture-dependent details for x86_64"""

    def __init__(self):
        # general purpose registers for 64bits
        self.gpr_64 = [
            "RAX",
            "RBX",
            "RCX",
            "RDX",
            "RSI",
            "RDIR9",
            "R10",
            "R11",
            "R12",
            "R13",
            "R14",
            "R15",
        ]

        self.gpr_32 = [
            "EAX",
            "EBX",
            "ECX",
            "EDX",
            "ESI",
            "EDI",
            "R8D",
            "R9D",
            "R10D",
            "R11D",
            "R12D",
            "R13D",
            "R14D",
            "R15D",
        ]

        self.gpr_16 = [
            "AX",
            "BX",
            "CX",
            "DX",
            "SI",
            "DI",
            "R8W",
            "R9W",
            "R10W",
            "R11W",
            "R12W",
            "R13W",
            "R14W",
            "R15W",
        ]

        self.gpr_8 = [
            "AL",
            "BL",
            "CL",
            "DL",
            "SIL",
            "DIL",
            "R8B",
            "R9B",
            "R10B",
            "R11B",
            "R12B",
            "R13B",
            "R14B",
            "R15B",
        ]

        self.fpu_x87 = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"]

        self.sse_xmm = [
            "XMM0",
            "XMM1",
            "XMM2",
            "XMM3",
            "XMM4",
            "XMM5",
            "XMM6",
            "XMM7",
            "XMM8",
            "XMM9",
            "XMM10",
            "XMM11",
            "XMM12",
            "XMM13",
            "XMM14",
            "XMM15",
        ]

        self.avx_ymm = [
            "YMM0",
            "YMM1",
            "YMM2",
            "YMM3",
            "YMM4",
            "YMM5",
            "YMM6",
            "YMM7",
            "YMM8",
            "YMM9",
            "YMM10",
            "YMM11",
            "YMM12",
            "YMM13",
            "YMM14",
            "YMM15",
        ]
        self.flags = ["FLAGS", "EFLAGS", "RFLAGS"]
        self.stack_registers = ["RBP", "RSP", "SP", "BP"]
        self.size = 8
        self.global_registers = (
            self.gpr_64
            + self.gpr_32
            + self.gpr_16
            + self.gpr_8
            + self.fpu_x87
            + self.sse_xmm
            + self.avx_ymm
        )
        self.opcode_categories = self._initialize_opcode_categories()

        ## instructions
        self.instructions = []

    def is_register(self, register):
        register = register.upper()
        return register in self.global_registers

    def is_general_purpose_register(self, register):
        register = register.upper()
        return (
            register in self.gpr_64
            or register in self.gpr_32
            or register in self.gpr_16
            or register in self.gpr_8
        )

    def is_stack_register(self, register):
        register = register.upper()
        return register in self.stack_registers

    def is_xmm_register(self, register):
        register = register.upper()
        return register in self.sse_xmm

    def is_control_flow(self, instr_tokens):
        return False

    def is_control_flow_instruction(self, instr_tokens):
        """Check if an instruction is a control flow instruction (jump, call, return, loop)."""
        try:
            # Extract the mnemonic from the instruction tokens
            mnemonic = None
            for token in instr_tokens:
                if token.type == InstructionTextTokenType.InstructionToken:
                    mnemonic = token.text.upper()
                    break

            if not mnemonic:
                return False

            # Check if it's a jump, call, return, or loop instruction
            return (
                mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
                or mnemonic == "CALL"  # Function calls
                or mnemonic == "RET"  # Return
                or mnemonic == "RETN"  # Another form of return
                or mnemonic.startswith("LOOP")
            )  # Loop instructions

        except Exception as e:
            print(e)
            # If we can't determine, assume it's not a control flow instruction
            return False

    def is_control_flow_instruction_by_mnemonic(self, mnemonic):
        """Check if an instruction is a control flow instruction based on its mnemonic."""
        if not mnemonic:
            return False

        mnemonic = mnemonic.upper()
        return (
            mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
            or mnemonic == "CALL"  # Function calls
            or mnemonic == "RET"  # Return
            or mnemonic == "RETN"  # Another form of return
            or mnemonic.startswith("LOOP")
        )

    def _initialize_opcode_categories(self):
        """Initialize mapping of opcodes to categories similar to Ghidra's implementation."""
        opcode_categories = {}
        opcode_index = {}  # Add this to mimic Ghidra's opcodeIndex

        # Define common opcodes array similar to Ghidra's COMMON_OPCODES
        COMMON_OPCODES = [
            # Core instructions (tracked individually)
            "MOV",
            "PUSH",
            "POP",
            "LEA",
            "CALL",
            "RET",  # Data movement and control
            "ADD",
            "SUB",
            "MUL",
            "DIV",  # Basic arithmetic
            "AND",
            "OR",
            "XOR",
            "NOT",  # Logical operations
            "JMP",
            "JE",
            "JNE",  # Basic jumps
            "TEST",
            "CMP",  # Comparisons
            # Grouped categories (aggregated tracking)
            "SIMD_MOVE",  # MOVAPS, MOVDQA, MOVDQU, etc.
            "COND_JUMP_EXT",  # Other conditional jumps (JG, JL, JGE, etc.)
            "STRING_OP",  # MOVS, STOS, LODS, SCAS, CMPS
            "STACK_ADV",  # ENTER, LEAVE, PUSHA, POPA
            "ARITHMETIC_ADV",  # IMUL, IDIV, ADC, SBB
            "BIT_OP",  # SHL, SHR, SAR, ROL, ROR, etc.
            "FPU_OP",  # FLD, FST, FADD, etc.
            "SYSTEM_OP",  # SYSCALL, INT, SYSENTER
            "CRYPTO_OP",  # AES*, SHA* instructions
            "MISC_OP",  # Rare but interesting (CPUID, RDTSC, etc.)
        ]

        # Create index map like Ghidra
        for i, opcode in enumerate(COMMON_OPCODES):
            opcode_index[opcode] = i

        # Now categorize opcodes using if/elif/else structure like in Ghidra
        for opcode in COMMON_OPCODES:
            # String Operations (checking these first to avoid MOV confusion)
            if opcode.startswith("MOVS") or opcode in [
                "STOS",
                "LODS",
                "SCAS",
                "CMPS",
                "REP",
                "REPE",
                "REPNE",
            ]:
                opcode_categories[opcode] = "STRING_MANIPULATION"

            # Data Movement (after string ops to avoid MOVS confusion)
            elif opcode.startswith("MOV") or opcode in ["LEA", "XCHG"]:
                opcode_categories[opcode] = "DATA_MOVEMENT"

            # Stack Operations
            elif opcode in ["PUSH", "POP", "ENTER", "LEAVE", "PUSHA", "POPA"]:
                opcode_categories[opcode] = "STACK_MANAGEMENT"

            # Control Flow (non-conditional)
            elif opcode in ["JMP", "CALL", "RET"]:
                opcode_categories[opcode] = "CONTROL_FLOW"

            # Conditional Jumps and Loops
            elif opcode.startswith("J") or opcode.startswith("LOOP"):
                opcode_categories[opcode] = "CONDITIONAL_JUMP"

            # Arithmetic
            elif opcode in [
                "ADD",
                "SUB",
                "MUL",
                "DIV",
                "IMUL",
                "IDIV",
                "ADC",
                "SBB",
                "INC",
                "DEC",
                "NEG",
            ]:
                opcode_categories[opcode] = "ARITHMETIC"

            # Logical
            elif opcode in ["AND", "OR", "XOR", "NOT", "TEST", "CMP"]:
                opcode_categories[opcode] = "LOGICAL"

            # Shifts & Rotates
            elif opcode in ["SHL", "SHR", "SAR", "SAL", "ROL", "ROR", "RCL", "RCR"]:
                opcode_categories[opcode] = "SHIFT_ROTATE"

            # System & Interrupts
            elif opcode in [
                "SYSCALL",
                "INT",
                "SYSENTER",
                "SYSEXIT",
                "SGDT",
                "SIDT",
                "SLDT",
                "WRMSR",
                "RDMSR",
            ]:
                opcode_categories[opcode] = "SYSTEM_CALLS"

            # Floating Point
            elif opcode.startswith("F"):
                opcode_categories[opcode] = "FPU_ARITHMETIC"

            # System Information and Random Number Generation
            elif opcode in ["PUSHF", "POPF", "CPUID", "RDTSC", "RDRAND", "RDSEED"]:
                opcode_categories[opcode] = "CPU_FEATURES"

            # Cryptography
            elif opcode.startswith("AES") or opcode.startswith("SHA"):
                opcode_categories[opcode] = "CRYPTOGRAPHIC"

            # Miscellaneous (including flag operations)
            else:
                opcode_categories[opcode] = "MISC"

        # Additional categorization for opcodes not in COMMON_OPCODES
        # This can be used in the normalize_opcode method

        # Store both maps as instance variables
        # self.opcode_categories = opcode_categories
        self.opcode_index = opcode_index

        return opcode_categories

    def is_simd_register(self, register):
        return register in self.sse_xmm