Indradeep Ghosh

55 papers A* 6A 5B 3C 3Misc 6Journal 17Unranked 14
YearRankTypeTitle / Venue / Authors
2022 — conf
Partitioning Dense Graphs with Hardware Accelerators.
ICCS (3)
Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2022 J jnl
Partitioning Dense Graphs with Hardware Accelerators.
CoRR
Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2022 Misc conf
Scaling Vehicle Routing Problem Solvers with QUBO-based Specialized Hardware.
SEC
Hanjing Xu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh
2022 — conf
Towards Practical Explainability with Cluster Descriptors.
ICDM (Workshops)
Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2022 J jnl
Towards Practical Explainability with Cluster Descriptors.
CoRR
Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro
2021 B conf
Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware.
IDA
Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh
2020 J jnl
Binary Matrix Factorization on Special Purpose Hardware.
CoRR
Osman Asif Malik, Hayato Ushijima-Mwesigwa, Arnab Roy, Avradip Mandal, Indradeep Ghosh
2020 J jnl
Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware.
CoRR
Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh
2017 J jnl
KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution.
IEEE Softw.
Hiroaki Yoshida, Guodong Li, Takuki Kamiya, Indradeep Ghosh, Sreeranga P. Rajan, Susumu Tokumoto, Kazuki Munakata, Tadahiro Uehara
2016 — conf
FSX: a tool for fine-grained incremental unit test generation for C/C++ programs.
SIGSOFT FSE
Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara
2016 A conf
FSX: fine-grained incremental unit test generation for C/C++ programs.
ISSTA
Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara
2015 A conf
Generating Succinct Test Cases Using Don't Care Analysis.
ICST
Cuong Nguyen, Hiroaki Yoshida, Mukul R. Prasad, Indradeep Ghosh, Koushik Sen
2014 — conf
SymJS: automatic symbolic testing of JavaScript web applications.
SIGSOFT FSE
Guodong Li, Esben Andreasen, Indradeep Ghosh
2013 A* conf
JST: an automatic test generation tool for industrial Java applications with strings.
ICSE
Indradeep Ghosh, Nastaran Shafiei, Guodong Li, Wei-Fan Chiang
2013 — conf
Lazy Symbolic Execution through Abstraction and Sub-space Search.
Haifa Verification Conference
Guodong Li, Indradeep Ghosh
2013 — conf
PASS: String Solving with Parameterized Array and Interval Automaton.
Haifa Verification Conference
Guodong Li, Indradeep Ghosh
2012 B conf
GKLEE: concolic verification and test generation for GPUs.
PPoPP
Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan
2011 A* conf
KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs.
CAV
Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan
2009 — conf
WEAVE: WEb Applications Validation Environment.
ICSE Companion
Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara
2008 B conf
Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution.
APLAS
Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid
2008 — book
Verification Techniques for System-Level Design.
Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad
2006 J jnl
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
2006 — conf
A Technique for Estimating the Difficulty of a Formal Verification Problem.
ISQED
Indradeep Ghosh, Mukul R. Prasad
2005 — conf
High Level Test Generation for Custom Hardware: An Industrial Perspective.
Asian Test Symposium
Indradeep Ghosh
2004 Misc conf
High Level Design Validation: Current Practices and Future Directions.
VLSI Design
Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita
2003 — conf
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.
Asian Test Symposium
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
2003 A conf
Efficient Sequential ATPG for Functional RTL Circuits.
ITC
Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
2003 — conf
Event-driven observability enhanced coverage analysis of C programs for functional validation.
ASP-DAC
Farzan Fallah, Indradeep Ghosh, Masahiro Fujita
2003 — conf
On automatic generation of RTL validation test benches using circuit testing techniques.
ACM Great Lakes Symposium on VLSI
Indradeep Ghosh, Srivaths Ravi
2003 C conf
Precomputation-based Guarding for Dynamic and Leakage Power Reduction.
ICCD
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
2002 — conf
Design for Verification at the Register Transfer Level.
ASP-DAC/VLSI Design
Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
2001 J jnl
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Masahiro Fujita
2001 J jnl
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
2001 — conf
Observability enhanced coverage analysis of C programs for functional validation.
HLDVT
Farzan Fallah, Indradeep Ghosh
2000 J jnl
A BIST scheme for RTL circuits based on symbolic testabilityanalysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
2000 C conf
A Technique for Identifying RTL and Gate-Level Correspondences.
ICCD
Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
2000 J jnl
A fast and low-cost testing technique for core-based system-chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
2000 A* conf
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams.
DAC
Indradeep Ghosh, Masahiro Fujita
2000 Misc conf
Hierarchical Error Diagnosis Targeting RTL Circuits.
VLSI Design
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
1999 J jnl
A low overhead design for testability and test generation technique for core-based systems-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1999 J jnl
Hierarchical test generation and design for testability methods for ASPPs and ASIPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1998 A* conf
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.
DAC
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
1998 A* conf
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip.
DAC
Indradeep Ghosh, Sujit Dey, Niraj K. Jha
1998 J jnl
A design-for-testability technique for register-transfer level circuits using control/data flow extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1998 J jnl
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.
J. Electron. Test.
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998 Misc conf
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.
VLSI Design
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998 J jnl
High-level test synthesis: a survey.
Integr.
Indradeep Ghosh, Niraj K. Jha
1997 A conf
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems.
ITC
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
1997 Misc conf
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.
VLSI Design
Sudipta Bhawmik, Indradeep Ghosh
1997 J jnl
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1997 A* conf
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.
DAC
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1996 A conf
A design for testability technique for RTL circuits using control/data flow extraction.
ICCAD
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1995 C conf
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
ICCD
Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
1995 J jnl
VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images.
Int. J. Pattern Recognit. Artif. Intell.
Indradeep Ghosh, Bandana Majumdar
1994 Misc conf
Design of an Application Specific VLSI Chip for Image Rotation.
VLSI Design
Indradeep Ghosh, Bandana Majumdar