In-Cheol Park - RankMe

208 papers A* 9A 7B 5C 27Misc 3Journal 103Unranked 54

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Hardware-Efficient Unified Approximation for Implementing Diverse Smooth Activation Functions. IEEE Trans. Computers Jeongmin Kim, Kangjoon Choi, In-Cheol Park
2026	J	`jnl`	Low-Complexity Bit-Error Rate Evaluation of Algebraic Codes. IEEE Commun. Lett. Jaehoon Kwon, Hansol Jeong, Jeongmin Kim, In-Cheol Park
2025	J	`jnl`	Energy-Efficient Syndrome Calculation Architecture for BCH Decoders. IEEE Trans. Very Large Scale Integr. Syst. Jeongmin Kim, Jaehoon Kwon, Hansol Jeong, In-Cheol Park
2025	J	`jnl`	Error Probability of Multi-Bit Nodes in Polar Codes Considering Effective Bit Count. IEEE Commun. Lett. Seungju Woo, Sungho Kim, Minha Park, In-Cheol Park
2025	J	`jnl`	Hardware-Efficient Architecture for Multiple Quantized Gaussian Noise Generation. IEEE Trans. Circuits Syst. I Regul. Pap. Kangjoon Choi, In-Cheol Park
2025	J	`jnl`	High-Speed CMOS Synchronous Binary Counter With Constant Counting Rate. IEEE Access Sungho Kim, Jeongmin Kim, In-Cheol Park
2025	J	`jnl`	Multi-Bit Successive Cancellation List Decoding of Polar Codes Using One-Bit Error Boundary. IEEE Commun. Lett. In-Cheol Park, Seungju Woo, Jaeyoung Lee, Minha Park, Sangbeom Park
2025	J	`jnl`	Multiple-Resolution Decoding Architecture for QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. In-Cheol Park, Kangjoon Choi, Hyejung Jang, Jongmin Baek
2024	J	`jnl`	Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting. IEEE Trans. Circuits Syst. I Regul. Pap. Boseon Jang, Hyejung Jang, Sungho Kim, Kangjoon Choi, In-Cheol Park
2024	J	`jnl`	Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation. IEEE Trans. Circuits Syst. I Regul. Pap. Jeongmin Kim, Sungho Kim, Kangjoon Choi, In-Cheol Park
2024	J	`jnl`	Hardware-Friendly Approximation for Swish Activation and Its Implementation. IEEE Trans. Circuits Syst. II Express Briefs Kangjoon Choi, Sungho Kim, Jeongmin Kim, In-Cheol Park
2023	J	`jnl`	A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Suchang Kim, Boseon Jang, Jaeyoung Lee, Hyungjoon Bae, Hyejung Jang, In-Cheol Park
2023	J	`jnl`	High-Speed Counter With Novel LFSR State Extension. IEEE Trans. Computers Hyungjoon Bae, Yujin Hyun, Suchang Kim, Sangsoo Park, Jaeyoung Lee, Boseon Jang, Suyoung Choi, In-Cheol Park
2022	J	`jnl`	In Situ Multi-Bit Decision for Successive Cancellation List Decoding of Polar Codes. IEEE Access Jaehyeon Park, Jaeyoung Lee, In-Cheol Park
2022	J	`jnl`	Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard. IEEE Trans. Circuits Syst. I Regul. Pap. Seongjin Lee, Sangsoo Park, Boseon Jang, In-Cheol Park
2021	J	`jnl`	Constant-Time Synchronous Binary Counter With Minimal Clock Period. IEEE Trans. Circuits Syst. II Express Briefs Yujin Hyun, In-Cheol Park
2021	J	`jnl`	Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. IEEE Trans. Circuits Syst. I Regul. Pap. Suchang Kim, Jihyuck Jo, In-Cheol Park
2021	J	`jnl`	Interleaved Local Sorting for Successive Cancellation List Decoding of Polar Codes. IEEE Access Wooyoung Kim, Yujin Hyun, Jaeyoung Lee, In-Cheol Park
2021	J	`jnl`	Real-Time SSDLite Object Detection on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Suchang Kim, Seungho Na, Byeong Yong Kong, Jaewoong Choi, In-Cheol Park
2020	C	`conf`	A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. ISCAS Byeong Yong Kong, In-Cheol Park
2020	J	`jnl`	A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. IEEE Trans. Circuits Syst. II Express Briefs Byeong Yong Kong, In-Cheol Park
2020	C	`conf`	A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. ISCAS Byeong Yong Kong, Jooseung Lee, In-Cheol Park
2020	J	`jnl`	A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. Byeong Yong Kong, Jooseung Lee, In-Cheol Park
2020	J	`jnl`	Large-Small Sorting for Successive Cancellation List Decoding of Polar Codes. IEEE Access Kyungpil Lee, In-Cheol Park
2020	J	`jnl`	Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Jaewoong Choi, Byeong Yong Kong, In-Cheol Park
2019	J	`jnl`	Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages. IEEE Trans. Circuits Syst. I Regul. Pap. Seokha Hwang, Seungsik Moon, Jaehwan Jung, Daesung Kim, In-Cheol Park, Jeongseok Ha, Youngjoo Lee
2019	—	`conf`	Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns. ICC Byeong Yong Kong, In-Cheol Park
2018	—	`conf`	A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. ASP-DAC Jaehwan Jung, In-Cheol Park, Youngjoo Lee
2018	J	`jnl`	A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion. IEEE Trans. Signal Process. Daesung Kim, In-Cheol Park
2018	J	`jnl`	A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading. IEEE J. Solid State Circuits Byeong Yong Kong, In-Cheol Park
2018	J	`jnl`	DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. IEEE J. Solid State Circuits Jihyuck Jo, Soyoung Cha, Dayoung Rho, In-Cheol Park
2018	—	`conf`	Efficient Implementation of Multiple Interleavers in IDMA for 5G. ISOCC Byeong Yong Kong, In-Cheol Park
2018	J	`jnl`	Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. Jihyuck Jo, Suchang Kim, In-Cheol Park
2018	J	`jnl`	Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture. IEEE Trans. Circuits Syst. II Express Briefs Daesung Kim, Injae Yoo, In-Cheol Park
2018	—	`conf`	Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. ICECS Byeong Yong Kong, Jaehwan Jung, In-Cheol Park
2017	—	`conf`	An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. A-SSCC Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee
2017	J	`jnl`	High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video. IEEE Trans. Circuits Syst. II Express Briefs Jooseung Lee, In-Cheol Park
2017	J	`jnl`	Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes. IEEE Commun. Lett. Saedong Yeo, In-Cheol Park
2017	J	`jnl`	Improved Sorting Architecture for K-Best MIMO Detection. IEEE Trans. Circuits Syst. II Express Briefs Byeong Yong Kong, In-Cheol Park
2017	J	`jnl`	Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition. IEEE Commun. Lett. Jaejoon Choi, In-Cheol Park
2017	J	`jnl`	Low-Latency Low-Cost Architecture for Square and Cube Roots. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jihyuck Jo, In-Cheol Park
2017	J	`jnl`	Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks. IEEE Trans. Circuits Syst. II Express Briefs Injae Yoo, In-Cheol Park
2017	J	`jnl`	Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems. IEEE Commun. Lett. Jaehwan Jung, In-Cheol Park
2016	J	`jnl`	Area-Efficient Approach for Generating Quantized Gaussian Noise. IEEE Trans. Circuits Syst. I Regul. Pap. Jaejoon Choi, Jaehwan Jung, In-Cheol Park
2016	J	`jnl`	Efficient Pruning for Successive-Cancellation Decoding of Polar Codes. IEEE Commun. Lett. Hoyoung Yoo, In-Cheol Park
2016	J	`jnl`	Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park
2016	J	`jnl`	Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. IEEE Trans. Very Large Scale Integr. Syst. Jihyuck Jo, Hoyoung Yoo, In-Cheol Park
2016	J	`jnl`	Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems. IEICE Trans. Electron. Youngjoo Lee, Jaehwan Jung, In-Cheol Park
2016	J	`jnl`	Low-Power Parallel Chien Search Architecture Using a Two-Step Approach. IEEE Trans. Circuits Syst. II Express Briefs Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2016	B	`conf`	Low-complexity symbol detection for massive MIMO uplink based on Jacobi method. PIMRC Byeong Yong Kong, In-Cheol Park
2015	J	`jnl`	Efficient Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2015	J	`jnl`	Low-Complexity Tree Architecture for Finding the First Two Minima. IEEE Trans. Circuits Syst. II Express Briefs Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park
2015	Misc	`conf`	Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation. ICASSP Byeong Yong Kong, In-Cheol Park
2015	J	`jnl`	Partially Parallel Encoder Architecture for Long Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs Hoyoung Yoo, In-Cheol Park
2015	J	`jnl`	Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Injae Yoo, Bongjin Kim, In-Cheol Park
2015	—	`conf`	Unidirectional ring ethernet for low-complexity in-vehicle control network. ICIT Injae Yoo, Mina Hwang, Jaehwan Jung, Suhyun Kim, In-Cheol Park
2014	—	`conf`	7.3 Gb/s universal BCH encoder and decoder for SSD controllers. ASP-DAC Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2014	—	`conf`	A search-less DEC BCH decoder for low-complexity fault-tolerant systems. SiPS Injae Yoo, In-Cheol Park
2014	J	`jnl`	High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
2014	J	`jnl`	Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang, Soyoung Cha, Bongjin Kim, In-Cheol Park
2014	J	`jnl`	Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Injae Yoo, Bongjin Kim, In-Cheol Park
2013	J	`jnl`	A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
2013	—	`conf`	A 3Gb/s 2.08mm ASP-DAC Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
2013	—	`conf`	Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors. VTC Spring Byeong Yong Kong, In-Cheol Park
2013	J	`jnl`	Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
2013	J	`jnl`	Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division. IEICE Trans. Commun. Bongjin Kim, In-Cheol Park
2013	J	`jnl`	Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization. IEEE Commun. Lett. Byeong Yong Kong, In-Cheol Park
2013	J	`jnl`	Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. IEEE Trans. Circuits Syst. II Express Briefs Bongjin Kim, Injae Yoo, In-Cheol Park
2013	—	`conf`	Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. VTC Spring Injae Yoo, Bongjin Kim, In-Cheol Park
2012	—	`conf`	6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. ISSCC Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
2012	J	`jnl`	FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Byeong Yong Kong, In-Cheol Park
2012	J	`jnl`	Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. IEEE Commun. Lett. Injae Yoo, Bongjin Kim, In-Cheol Park
2012	J	`jnl`	Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems. IEEE Trans. Very Large Scale Integr. Syst. Kangwoo Park, In-Cheol Park
2012	—	`conf`	Low-latency area-efficient decoding architecture for shortened reed-solomon codes. ISOCC Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
2012	—	`conf`	SNR-Adaptive Input Quantization for Turbo Decoding. VTC Spring Injae Yoo, In-Cheol Park
2012	Misc	`conf`	Small-area parallel syndrome calculation for strong BCH decoding. ICASSP Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
2011	—	`conf`	Division-less high-radix interleaved modular multiplication using a scaled modulus. ISOCC Jinook Song, In-Cheol Park
2011	J	`jnl`	Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration. IEICE Trans. Commun. Tae-Hwan Kim, In-Cheol Park
2011	J	`jnl`	Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. IEEE Trans. Circuits Syst. II Express Briefs Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
2011	C	`conf`	QC-LDPC Decoding Architecture based on Stride Scheduling. ISCAS Bongjin Kim, In-Cheol Park
2011	—	`conf`	Statistical modeling of capacitor mismatch effects for successive approximation register ADCs. ISOCC Youngjoo Lee, Jinook Song, In-Cheol Park
2010	—	`conf`	A 2.6Gb/s 1.56mm CICC Tae-Hwan Kim, In-Cheol Park
2010	C	`conf`	Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters. ISCAS Youngjoo Lee, In-Cheol Park
2010	J	`jnl`	Design of a Scalable and Programmable Sound Synthesizer. IEEE Trans. Very Large Scale Integr. Syst. Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park
2010	C	`conf`	Dual-rail decoding of low-density parity-check codes. ISCAS Bongjin Kim, Hasan Ahmed, In-Cheol Park
2010	J	`jnl`	High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search. IEEE Trans. Circuits Syst. I Regul. Pap. Tae-Hwan Kim, In-Cheol Park
2010	—	`conf`	Low-complex BPSK demodulation using absolute comparison. ICECS Youngjoo Lee, Goeun Lim, In-Cheol Park
2010	C	`conf`	Low-complexity tone reservation method for PAPR reduction of OFDM systems. ISCAS Kangwoo Park, In-Cheol Park
2010	J	`jnl`	Multiplier-less and Table-less Linear Approximation for Square-Related Functions. IEICE Trans. Inf. Syst. In-Cheol Park, Tae-Hwan Kim
2010	J	`jnl`	Optimization of Arithmetic Coding for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. Minsoo Rhu, In-Cheol Park
2010	J	`jnl`	Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding. IEEE Trans. Circuits Syst. I Regul. Pap. Tae-Hwan Kim, In-Cheol Park
2010	A	`conf`	Small-area and low-energy ISLPED Tae-Hwan Kim, In-Cheol Park
2010	J	`jnl`	Spur-Free MASH Delta-Sigma Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. Jinook Song, In-Cheol Park
2009	C	`conf`	A Scalable and Programmable Sound Synthesizer. ISCAS Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park
2009	—	`conf`	A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. SiPS Minsoo Rhu, In-Cheol Park
2009	—	`conf`	A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE. CICC Ji-Hoon Kim, In-Cheol Park
2009	B	`conf`	Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000. ICIP Minsoo Rhu, In-Cheol Park
2009	J	`jnl`	Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes. IEEE Trans. Circuits Syst. II Express Briefs Ji-Hoon Kim, In-Cheol Park
2009	C	`conf`	Fast Frequency Acquisition Phase Frequency Detectors with Prediction-based edge Blocking. ISCAS Kangwoo Park, In-Cheol Park
2009	B	`conf`	Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search. GLOBECOM Tae-Hwan Kim, In-Cheol Park
2009	B	`conf`	Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding. ICIP Minsoo Rhu, In-Cheol Park
2009	C	`conf`	Multiplier-less and table-less linear approximation for square and square-root. ICCD In-Cheol Park, Tae-Hwan Kim
2009	C	`conf`	Novel Pipelined DWT Architecture for Dual-line Scan. ISCAS Jinook Song, In-Cheol Park
2009	J	`jnl`	Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines. IEEE Trans. Circuits Syst. II Express Briefs Jinook Song, In-Cheol Park
2008	—	`conf`	Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. ASP-DAC Tae-Hwan Kim, In-Cheol Park
2008	C	`conf`	Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. ISCAS Jeong-Sup Lee, In-Cheol Park
2008	C	`conf`	Digital filter synthesis considering multiple adder graphs for a coefficient. ICCD Jeong-Ho Han, In-Cheol Park
2008	J	`jnl`	Double-Binary Circular Turbo Decoding Based on Border Metric Encoding. IEEE Trans. Circuits Syst. II Express Briefs Ji-Hoon Kim, In-Cheol Park
2008	—	`conf`	Duo-binary circular turbo decoder based on border metric encoding for WiMAX. ASP-DAC Ji-Hoon Kim, In-Cheol Park
2008	J	`jnl`	FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeong-Ho Han, In-Cheol Park
2008	C	`conf`	Fast frequency acquisition all-digital PLL using PVT calibration. ISCAS Hae-Soo Jeon, Duk-Hyun You, In-Cheol Park
2008	J	`jnl`	Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems. IEEE Trans. Very Large Scale Integr. Syst. Tae-Hwan Kim, In-Cheol Park
2008	C	`conf`	Prediction-based real-time CABAC decoder for high definition H.264/AVC. ISCAS WonHee Son, In-Cheol Park
2008	—	`conf`	Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset. VTC Spring Tae-Hwan Kim, In-Cheol Park
2007	J	`jnl`	Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing. IEEE Trans. Circuits Syst. I Regul. Pap. Hyun-Yong Lee, In-Cheol Park
2007	C	`conf`	Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. ISCAS Ji-Hoon Kim, In-Cheol Park
2007	—	`conf`	Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. VTC Spring Se-Hyeon Kang, In-Cheol Park
2007	C	`conf`	High Speed Sphere Decoding Based on Vertically Incremental Computation. ISCAS Se-Hyeon Kang, In-Cheol Park
2007	J	`jnl`	High-Speed H.264/AVC CABAC Decoding. IEEE Trans. Circuits Syst. Video Technol. Y. Yi, In-Cheol Park
2007	J	`jnl`	Long-Point FFT Processing Based on Twiddle Factor Table Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ji-Hoon Kim, In-Cheol Park
2007	J	`jnl`	Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction. IEICE Trans. Inf. Syst. Chung-Hyo Kim, In-Cheol Park
2007	J	`jnl`	Pipelined Cartesian-to-Polar Coordinate Conversion Based on SRT Division. IEEE Trans. Circuits Syst. II Express Briefs Sung-Won Lee, Ki-Seok Kwon, In-Cheol Park
2007	J	`jnl`	SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. IEEE Trans. Very Large Scale Integr. Syst. Myoung-Cheol Shin, In-Cheol Park
2007	C	`conf`	Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. ISCAS Jung-Wook Kim, Jinook Song, Seokho Lee, In-Cheol Park
2007	C	`conf`	Twiddle factor transformation for pipelined FFT processing. ICCD In-Cheol Park, WonHee Son, Ji-Hoon Kim
2007	—	`conf`	Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems. SiPS Tae-Hwan Kim, In-Cheol Park
2006	C	`conf`	Combined image signal processing for CMOS image sensors. ISCAS Kimo Kim, In-Cheol Park
2006	C	`conf`	High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction. ISCAS Chung-Hyo Kim, In-Cheol Park
2006	J	`jnl`	Loosely coupled memory-based decoding architecture for low density parity check codes. IEEE Trans. Circuits Syst. I Regul. Pap. Se-Hyeon Kang, In-Cheol Park
2006	J	`jnl`	Low-Power Hybrid Turbo Decoding Based on Reverse Calculation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park
2006	C	`conf`	Low-power hybrid turbo decoding based on reverse calculation. ISCAS Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park
2006	J	`jnl`	Low-power log-MAP decoding based on reduced metric memory access. IEEE Trans. Circuits Syst. I Regul. Pap. Dong-Soo Lee, In-Cheol Park
2005	J	`jnl`	A Low-Complexity Stopping Criterion for Iterative Turbo Decoding. IEICE Trans. Commun. Dong-Soo Lee, In-Cheol Park
2005	—	`conf`	A scalable SIMD digital signal processor for high-quality multifunctional printer systems. Color Imaging: Processing, Hardcopy, and Applications Hyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang
2005	J	`jnl`	A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005	J	`jnl`	Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005	J	`jnl`	Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005	—	`conf`	Loosely coupled memory-based decoding architecture for low density parity check codes. CICC Se-Hyeon Kang, In-Cheol Park
2005	—	`conf`	Low-power log-MAP turbo decoding based on reduced metric memory access. ISCAS (4) Dong-Soo Lee, In-Cheol Park
2005	J	`jnl`	Performance enhancement of embedded software based on new register allocation technique. Microprocess. Microsystems Jong-Yeol Lee, Seong Ik Cho, In-Cheol Park
2005	J	`jnl`	SAT-based unbounded symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyeong-Ju Kang, In-Cheol Park
2005	—	`conf`	Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. ISCAS (6) In-Cheol Park, Se-Hyeon Kang
2004	—	`conf`	A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors. CICC Young-Don Bae, In-Cheol Park
2004	—	`conf`	A fast Reed-Solomon Product-Code decoder without redundant computations. ISCAS (2) Hyun-Yong Lee, In-Cheol Park
2004	—	`conf`	Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. ISCAS (2) Se-Hyeon Kang, In-Cheol Park
2004	—	`conf`	Quadrature direct digital frequency synthesis using fine-grain angle rotation. ISCAS (2) Sung-Won Lee, In-Cheol Park
2003	—	`conf`	A 24-bit floating-point audio DSP controller supporting fast exponentiation. ISCAS (2) Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park
2003	—	`conf`	A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) Hyung Ki Ahn, In-Cheol Park, Beomsup Kim
2003	—	`conf`	A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2003	J	`jnl`	A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords. IEEE Trans. Circuits Syst. II Express Briefs Sung-Won Lee, In-Cheol Park
2003	J	`jnl`	A single-chip programmable platform based on a multithreaded processor and configurable logic clusters. IEEE J. Solid State Circuits Young-Don Bae, Seong-Il Park, In-Cheol Park
2003	J	`jnl`	Address code generation for DSP instruction-set architectures. ACM Trans. Design Autom. Electr. Syst. Jong-Yeol Lee, In-Cheol Park
2003	—	`conf`	Area-efficient memory-based architecture for FFT processing. ISCAS (5) Sang-Chul Moon, In-Cheol Park
2003	A	`conf`	Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. ICCAD In-Cheol Park, Se-Hyeon Kang, Yongseok Yi
2003	J	`jnl`	High performance memory mode control for HDTV decoders. IEEE Trans. Consumer Electron. Seong-Il Park, Yongseok Yi, In-Cheol Park
2003	—	`conf`	History-based memory mode prediction for improving memory performance. ISCAS (5) Seong-Il Park, In-Cheol Park
2003	—	`conf`	Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems. ICASSP (2) Sung-Won Lee, In-Cheol Park
2003	A	`conf`	Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems. ICME Sung-Won Lee, In-Cheol Park
2003	—	`conf`	Pairing and ordering to reduce hardware complexity in cascade form filter design. ISCAS (4) Hyeong-Ju Kang, In-Cheol Park
2003	J	`jnl`	Processor-based turbo interleaver for multiple third-generation wireless standards. IEEE Commun. Lett. Myoung-Cheol Shin, In-Cheol Park
2003	A*	`conf`	SAT-based unbounded symbolic model checking. DAC Hyeong-Ju Kang, In-Cheol Park
2003	J	`jnl`	Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jong-Yeol Lee, In-Cheol Park
2002	Misc	`conf`	A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. ICASSP Hyeong-Ju Kang, In-Cheol Park
2002	J	`jnl`	An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chang-Jae Park, Ando Ki, In-Cheol Park, Chong-Min Kyung
2002	—	`conf`	Area-efficient digital baseband module for Bluetooth wireless communications. ISCAS (5) Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park
2002	J	`jnl`	Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. In-Cheol Park, Hyeong-Ju Kang
2002	J	`jnl`	Interface synthesis between software chip model and target board. J. Syst. Archit. Seungjong Lee, Ando Ki, In-Cheol Park, Chong-Min Kyung
2002	J	`jnl`	Loop and Address Code Optimization for Digital Signal Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jong-Yeol Lee, In-Cheol Park
2002	—	`conf`	Low cost floating-point unit design for audio applications. ISCAS (1) Sung-Won Lee, In-Cheol Park
2002	A*	`conf`	Timed compiled-code simulation of embedded software for performance analysis of SOC design. DAC Jong-Yeol Lee, In-Cheol Park
2001	J	`jnl`	A fixed-point MPEG audio processor operating at low frequency. IEEE Trans. Consumer Electron. Yongseok Yi, In-Cheol Park
2001	—	`conf`	A low-power variable length decoder based on successive decoding of shoft codewords. ISCAS (4) Sung-Won Lee, In-Cheol Park
2001	C	`conf`	An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. ICCD Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
2001	A*	`conf`	Digital Filter Synthesis Based on Minimal Signed Digit Representation. DAC In-Cheol Park, Hyeong-Ju Kang
2001	—	`conf`	Global variable localization and transformation for hardware synthesis from high-level programming language description. ISCAS (5) Jong-Yeol Lee, In-Cheol Park
2001	J	`jnl`	High-performance and low-power memory-interface architecture for video processing applications. IEEE Trans. Circuits Syst. Video Technol. Hansoo Kim, In-Cheol Park
2001	—	`conf`	Low-power high-level synthesis using latches. ASP-DAC Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung
2001	—	`conf`	Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ISCAS (2) Hyeong-Ju Kang, In-Cheol Park
2000	—	`conf`	A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. ASP-DAC Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
2000	C	`conf`	Array address translation for SDRAM-based video processing applications. VCIP Hansoo Kim, In-Cheol Park
2000	A	`conf`	FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. ICCAD Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
2000	J	`jnl`	MetaCore: an application-specific programmable DSP development system. IEEE Trans. Very Large Scale Integr. Syst. Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
2000	—	`conf`	Multi-thread VLIW processor architecture for HDTV decoding. CICC Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park
2000	C	`conf`	Optimal down-conversion in compressed DCT domain with minimal operations. VCIP Myoung-Cheol Shin, In-Cheol Park
2000	B	`conf`	Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. ICIP Young-Su Kwon, In-Cheol Park, Chong-Min Kyung
2000	C	`conf`	Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. ICCD Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung
1999	—	`conf`	A New Single-Clock Flip-Clop for Half-Swing Clocking. ASP-DAC Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
1999	C	`conf`	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. ICCD Bong-Il Park, In-Cheol Park, Chong-Min Kyung
1999	C	`conf`	Customization of a CISC Processor Core for Low-Power Applications. ICCD You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung
1999	A*	`conf`	Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. DAC Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung
1999	—	`conf`	Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. ASP-DAC Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
1999	J	`jnl`	Path-based branch prediction using signature analysis. Microprocess. Microsystems Seunjeogn Lee, In-Cheol Park, Chong-Min Kyung
1999	J	`jnl`	Synthesis of Application Specific Instructions for Embedded DSP Software. IEEE Trans. Computers Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
1999	A*	`conf`	Verification of a Microprocessor Using Real World Applications. DAC You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung
1998	A*	`conf`	MetaCore: An Application Specific DSP Development System. DAC Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung
1998	A	`conf`	Multiple Behavior Module Synthesis Based on Selective Groupings. DATE Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
1998	A	`conf`	Synthesis of application specific instructions for embedded DSP software. ICCAD Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park
1998	A*	`conf`	Virtual Chip: Making Functional Models Work on Real Target Systems. DAC Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung
1997	A*	`conf`	A C-Based RTL Design Verification Methodology for Complex Microprocessor. DAC Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung
1997	J	`jnl`	Design Verification of Complex Microprocessors. J. Circuits Syst. Comput. Joon-Seo Yim, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung
1997	—	`conf`	HK386: an x86-compatible 32-bit CISC microprocessor. ASP-DAC Chong-Min Kyung, In-Cheol Park, Se-Kyoung Hong, K. S. Seong, B. S. Kong, Seungjong Lee, Hoon Choi, S. R. Maeng, D. T. Kim, Jong-Sun Kim, S. H. Park, Y. J. Kang
1997	—	`conf`	Multi-project chip activities in Korea-IDEC perspective. ASP-DAC Chong-Min Kyung, In-Cheol Park, Ho-Jun Song
1997	—	`conf`	Single cycle access cache for the misaligned data and instruction prefetch. ASP-DAC Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-Il Park, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung
1997	—	`conf`	Verification methodology of compatible microprocessors. ASP-DAC Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung
1994	J	`jnl`	Two Complementary Approaches for Microcode Bit Optimization. IEEE Trans. Computers In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung
1993	J	`jnl`	FAMOS: an efficient scheduling algorithm for high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. In-Cheol Park, Chong-Min Kyung
1991	A*	`conf`	Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. DAC In-Cheol Park, Chong-Min Kyung
1990	A	`conf`	An O( ICCAD Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung