Ilya Tuzov

15 papers A 4B 1Misc 5Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2023 B conf
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.
ETS
Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric
2023 A conf
BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes.
DATE
Ilya Tuzov, David de Andrés, Juan-Carlos Ruiz-Garcia, Carles Hernández
2022 Misc conf
Reversing FPGA architectures for speeding up fault injection: does it pay?
EDCC
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2022 — conf
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs.
ARCS
Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener
2021 A conf
Improving the Robustness of Redundant Execution with Register File Randomization.
ICCAD
Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández
2020 Misc conf
Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems.
EDCC
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2019 Misc conf
Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs.
EDCC
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2019 J jnl
Simulating the effects of logic faults in implementation-level VITAL-compliant models.
Computing
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2018 Misc conf
Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection.
EDCC
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2018 A conf
DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models.
DSN
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2018 — conf
Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection.
LADC
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2018 J jnl
Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study.
J. Parallel Distributed Comput.
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2017 Misc conf
Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level.
EDCC
Ilya Tuzov, Juan Carlos Ruiz, David de Andrés
2017 A conf
Dependability-Aware Design Space Exploration for Optimal Synthesis Parameters Tuning.
DSN
Ilya Tuzov, David de Andrés, Juan Carlos Ruiz
2016 — conf
Speeding-Up Simulation-Based Fault Injection of Complex HDL Models.
LADC
Ilya Tuzov, Juan Carlos Ruiz, David de Andrés, Pedro J. Gil