Ilan Y. Spillinger

20 papers A* 2A 4Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2000 J jnl
Guest Editors' Introduction.
J. Instr. Level Parallelism
Ilan Y. Spillinger, Chris J. Newburn
1999 A* ed.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999
MICRO
Ronny Ronen, Matthew K. Farrens, Ilan Y. Spillinger
1996 J jnl
Retiming revisited and reversed.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guy Even, Ilan Y. Spillinger, Leon Stok
1995 — conf
Improving initialization through reversed retiming.
ED&TC
Leon Stok, Ilan Y. Spillinger, Guy Even
1994 J jnl
A backtracing-oriented procedure for the analysis of combinational gate-level designs.
Integr.
Gabriel M. Silberman, Ilan Y. Spillinger
1994 J jnl
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers.
IEEE Trans. Computers
Gideon D. Intrater, Ilan Y. Spillinger
1993 J jnl
Architectural Improvement for a Data-Driven VLSI Processing Array.
J. Parallel Distributed Comput.
Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
1993 J jnl
Linear test sequences for detecting functionally faulty RAM's.
Integr.
Guy Even, Ophir Rachman, Ilan Y. Spillinger
1992 A* conf
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers.
ISCA
Gideon D. Intrater, Ilan Y. Spillinger
1991 J jnl
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.
IEEE Trans. Computers
Gabriel M. Silberman, Ilan Y. Spillinger
1991 J jnl
RIDDLE: A Foundation for Test Generation on a High-Level Design Description.
IEEE Trans. Computers
Gabriel M. Silberman, Ilan Y. Spillinger
1990 J jnl
Using functional fault simulation and the difference fault model to estimate implementation fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gabriel M. Silberman, Ilan Y. Spillinger
1989 — conf
Architectural Improvements for Data-Driven VLSI Processing Arrays.
FPCA
Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
1989 J jnl
Whistle: A Workbench for Test Development of Library-Based Designs.
Computer
Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger
1988 A conf
Delay Test Generation 1: Concepts and Coverage Metrics.
ITC
Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
1988 A conf
Delay Test Generation 2: Algebra and Algorithms.
ITC
Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
1988 A conf
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing.
ITC
Gabriel M. Silberman, Ilan Y. Spillinger
1988 — conf
RIDDLE: a foundation for test generation on a high level design description.
FTCS
Gabriel M. Silberman, Ilan Y. Spillinger
1986 J jnl
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ilan Y. Spillinger, Gabriel M. Silberman
1986 A conf
The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage.
ITC
Gabriel M. Silberman, Ilan Y. Spillinger