Ik Joon Chang

37 papers A* 1A 4C 4Journal 21Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Post-Training Quantization via Residual Truncation and Zero Suppression for Diffusion Models.
CoRR
Donghoon Kim, Dongyoung Lee, Ik Joon Chang, Sung-Ho Bae
2025 J jnl
Qrazor: Reliable and effortless 4-bit llm quantization by significant data razoring.
CoRR
Dongyoung Lee, Seungkyu Choi, Ik Joon Chang
2025 — conf
SAPIENS: Towards Energy-efficient Deep Spiking Neural Networks via the Approximation of Power-expensive Neurons.
AICAS
Cheol-Min Kang, Nguyen-Dong Ho, Dongyoung Lee, Yonghwan Kwon, Donghyun Kim, Inhan Kang, Ik Joon Chang
2024 J jnl
FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Acceleration.
CoRR
Donghyeon Yi, Seoyoung Lee, Jongho Kim, Junyoung Kim, Sohmyung Ha, Ik Joon Chang, Minkyu Je
2021 A conf
Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks.
DATE
Nhut-Minh Ho, Duy Thanh Nguyen, Himeshi De Silva, John L. Gustafson, Weng-Fai Wong, Ik Joon Chang
2020 J jnl
A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems.
Sensors
Duckhoon Ro, Changhong Min, Myounggon Kang, Ik Joon Chang, Hyung-Min Lee
2020 A conf
PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training.
DATE
Boyeal Kim, Sang Hyun Lee, Hyun Kim, Duy Thanh Nguyen, Minh-Son Le, Ik Joon Chang, Dohun Kwon, Jin Hyeok Yoo, Jun Won Choi, Hyuk-Jae Lee
2018 C conf
An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications.
ISCAS
Duy Thanh Nguyen, Hyun Kim, Hyuk-Jae Lee, Ik Joon Chang
2018 J jnl
Optimal Selection of SRAM Bit-Cell Size for Power Reduction in Video Compression.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hyun Kim, Ik Joon Chang, Hyuk-Jae Lee
2017 J jnl
Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation.
Circuits Syst. Signal Process.
Ik Joon Chang, Sang Yoon Park, Jun Won Choi
2016 C conf
An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder.
ICCE
Hyun Kim, Ik Joon Chang, Hyuk-Jae Lee
2016 — conf
Architecture of WLAN channel estimators.
APCCAS
My-Kieu Nguyen-Thi, Ik Joon Chang, Jinsang Kim
2016 J jnl
Optimal reference view selection algorithm for low complexity disparity estimation.
IEEE Trans. Consumer Electron.
Minsu Choi, Ik Joon Chang, Jinsang Kim
2016 J jnl
Subthreshold 8T SRAM sizing utilizing short-channel V
IEICE Electron. Express
Ik Joon Chang, Joon-Sung Yang
2015 — conf
Low power block matching using pattern based pixel truncation.
MWSCAS
Minsu Choi, Kyung-Rae Kim, Ik Joon Chang, Jinsang Kim
2015 J jnl
SET-Tolerant Active Body-Bias Circuits in PD-SOI CMOS Technology.
IEICE Trans. Electron.
Youngkyu Jang, Ik Joon Chang, Jinsang Kim
2015 J jnl
Variation-Aware Flip Flop for DVFS Applications.
IEICE Trans. Electron.
Youngkyu Jang, Changnoh Yoon, Ik Joon Chang, Jinsang Kim
2014 J jnl
CPAC: Energy-Efficient Data Collection through Adaptive Selection of Compression Algorithms for Sensor Networks.
Sensors
HyungJune Lee, Hyunseok Kim, Ik Joon Chang
2014 A conf
a-SAD: power efficient SAD calculator for real time H.264 video encoder using MSB-approximation technique.
ISLPED
Trang Le Dinh Dang, Ik Joon Chang, Jinsang Kim
2013 J jnl
A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 µm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ngoc Dang Phan, Ik Joon Chang, Jong-Wook Lee
2013 J jnl
High Performance and Hardware Efficient Multiview Video Coding Frame Scheduling Algorithms and Architectures.
IEEE Trans. Circuits Syst. Video Technol.
Minsu Choi, Ik Joon Chang, Jinsang Kim
2013 C conf
Low complexity image correction using color and focus matching for stereo video coding.
ISCAS
Wooseok Kim, Joohan Kim, Minsu Choi, Ik Joon Chang, Jinsang Kim
2013 C conf
Low-complexity decision directed method for carrier frequency offset estimation of IEEE 802.11ad.
ISCAS
Junghyun Ha, Janghyuk Yoon, Ik Joon Chang, Jinsang Kim
2013 J jnl
Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion.
IEICE Trans. Electron.
Joon-Sung Yang, Ik Joon Chang
2012 — conf
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology.
ISSCC
Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byungjun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, AnSoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, HooSung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun
2012 J jnl
Bit-error rate improvement of TLC NAND Flash using state re-ordering.
IEICE Electron. Express
Ik Joon Chang, Joon-Sung Yang
2012 J jnl
Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinmo Kwon, Ik Joon Chang, Insoo Lee, Heemin Park, Jongsun Park
2012 — conf
Low-complexity frame scheduler using shared frame memory for multi-view video coding.
ISOCC
Minsu Choi, Jinsang Kim, Ik Joon Chang, Won-Kyung Cho
2011 J jnl
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol.
Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2011 J jnl
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V.
IEEE Trans. Very Large Scale Integr. Syst.
Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy
2010 J jnl
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.
IEEE J. Solid State Circuits
Ik Joon Chang, Sang Phill Park, Kaushik Roy
2010 J jnl
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst.
Ik Joon Chang, Jongsun Park, Kunhyuk Kang, Kaushik Roy
2009 J jnl
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.
IEEE J. Solid State Circuits
Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2009 A* conf
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
DAC
Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2008 — conf
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.
ISSCC
Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2006 A conf
Robust level converter design for sub-threshold logic.
ISLPED
Ik Joon Chang, Jae-Joon Kim, Kaushik Roy
2005 — conf
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
CICC
Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy