Ik-Joon Chang - RankMe

36 papers A* 4A 1C 1Journal 17Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Spike Sorting SoC With Δ-Based Spike Detection and End-to-End Implementation of Autoencoder Feature Extraction Using Analog CIM. IEEE J. Solid State Circuits Vincent Lukito, Edward Jongyoon Choi, Ik-Joon Chang, Sohmyung Ha, Minkyu Je
2025	—	`conf`	A 94.76%-accuracy, <16μs/classification-latency STT-MRAM CiM-based Classifier for Closed-loop Peripheral Nerve Modulation Implants. AICAS Seoyoung Lee, Donghyeon Yi, Edward Choi, Vincent Lukito, Jongho Kim, Ryan G. L. Koh, Sohmyung Ha, Ik-Joon Chang, Minkyu Je
2025	J	`jnl`	PABLO: A Variation-Robust PIM Architecture for Bulk Bitwise Logical Operations in DRAM. IEEE Trans. Emerg. Top. Comput. Minh-Son Le, Thanh-Dat Nguyen, Jeong Hoan Park, Seungkyu Choi, Ik-Joon Chang
2025	J	`jnl`	STT-HDC: An Efficient Time-Domain In-Memory Hyper-Dimensional Computing Design Based on STT-MRAM. IEEE Access Thi-Nhan Pham, Quang-Kien Trinh, Thanh-Dat Nguyen, Ik-Joon Chang
2024	—	`conf`	A 639.38GOPS Hybrid-Domain Logic-Compatible Multi-Level Embedded Flash Computing-in-Memory Macro with Spike-Edge Computation. A-SSCC Jiho Chun, Edward Choi, Byeongseon Choi, Donghyeon Yi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je
2024	—	`conf`	A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch. VLSI Technology and Circuits Edward Choi, Vincent Lukito, Injun Choi, Seoyoung Lee, Ik-Joon Chang, Sohmyung Ha, Minkyu Je
2024	—	`conf`	An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm ISOCC Edward Jongyoon Choi, Jiho Chun, Byeongseon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je
2024	A*	`conf`	MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy. DAC Nguyen-Dong Ho, Gyujun Jeong, Cheol-Min Kang, Seungkyu Choi, Ik-Joon Chang
2024	J	`jnl`	Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights. IEEE Trans. Circuits Syst. I Regul. Pap. Donghyeon Yi, Seoyoung Lee, Injun Choi, Gichan Yun, Edward Jongyoon Choi, Jonghee Park, Jonghoon Kwak, Sung-Joon Jang, Sohmyung Ha, Ik-Joon Chang, Minkyu Je
2024	J	`jnl`	TRIO-TCAM: An Area and Energy-Efficient Triple-State-in-Cell Ternary Content-Addressable Memory Architecture. IEEE Access Thanh-Dat Nguyen, Sungju Ryu, Ik-Joon Chang
2023	—	`conf`	A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation. CICC Edward Choi, Injun Choi, Vincent Lukito, Dong-Hwi Choi, Donghyeon Yi, Ik-Joon Chang, Sohmyung Ha, Minkyu Je
2023	J	`jnl`	Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements. IEEE Trans. Circuits Syst. II Express Briefs Young-Min Kang, Jung-Jin Park, Geon-Hak Kim, Ik-Joon Chang, Jinsang Kim
2023	J	`jnl`	MiCE: An ANN-to-SNN Conversion Technique to Enable High Accuracy and Low Latency. IEEE J. Emerg. Sel. Topics Circuits Syst. Nguyen-Dong Ho, Ik-Joon Chang
2023	J	`jnl`	O-2A: Outlier-Aware Compression for 8-bit Post-Training Quantization Model. IEEE Access Nguyen-Dong Ho, Ik-Joon Chang
2023	—	`conf`	TRIO: a Novel 10T Ternary SRAM Cell for Area-Efficient In-memory Computing of Ternary Neural Networks. AICAS Thanh-Dat Nguyen, Minh-Son Le, Thi-Nhan Pham, Ik-Joon Chang
2023	—	`conf`	Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. ICEIC Jung-Jin Park, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang, Jinsang Kim
2022	—	`conf`	A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. CICC Edward Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je
2022	J	`jnl`	An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO. IEEE J. Emerg. Sel. Topics Circuits Syst. Injun Choi, Edward Jongyoon Choi, Donghyeon Yi, Yoontae Jung, Hoyong Seong, Hyuntak Jeon, Soon-Jae Kweon, Ik-Joon Chang, Sohmyung Ha, Minkyu Je
2022	J	`jnl`	STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Thi-Nhan Pham, Quang-Kien Trinh, Ik-Joon Chang, Massimo Alioto
2021	J	`jnl`	OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems. Sensors Duy Thanh Nguyen, Nhut-Minh Ho, Weng-Fai Wong, Ik-Joon Chang
2021	J	`jnl`	PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory. CoRR Minh-Son Le, Thi-Nhan Pham, Thanh-Dat Nguyen, Ik-Joon Chang
2021	C	`conf`	STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks. ISCAS Thi-Nhan Pham, Kien Trinh Quang, Ik-Joon Chang, Massimo Alioto
2021	A*	`conf`	TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers. DAC Nguyen-Dong Ho, Ik-Joon Chang
2021	J	`jnl`	ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM. IEEE Access Duy Thanh Nguyen, Nhut-Minh Ho, Minh-Son Le, Weng-Fai Wong, Ik-Joon Chang
2020	—	`conf`	Comparing Variation-tolerance and SEU/TID-Resilience of Three SRAM Cells in 28nm FD-SOI Technology: 6T, Quatro, and we-Quatro. IRPS Trang Le Dinh Dang, Trinh Dinh Linh, Ngyuen Thanh Dat, Changhong Min, Jinsang Kim, Ik-Joon Chang, Jin-Woo Han
2020	A	`conf`	DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System. ICCAD Duy Thanh Nguyen, Changhong Min, Nhut-Minh Ho, Ik-Joon Chang
2020	A*	`conf`	O-2A: Low Overhead DNN Compression with Outlier-Aware Approximation. DAC Nguyen-Dong Ho, Minh-Son Le, Ik-Joon Chang
2020	J	`jnl`	TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers. CoRR Nguyen-Dong Ho, Ik-Joon Chang
2019	—	`conf`	Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection. ISOCC Duy Thanh Nguyen, Ik-Joon Chang
2019	J	`jnl`	Segmented Tag Cache: A Novel Cache Organization for Reducing Dynamic Read Energy. IEEE Trans. Computers Moonsoo Kim, Ik-Joon Chang, Hyuk-Jae Lee
2019	A*	`conf`	St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs. DAC Duy Thanh Nguyen, Nhut-Minh Ho, Ik-Joon Chang
2018	—	`conf`	A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 ~ 1V Wide Dynamic Voltage Scaling for Space Applications. A-SSCC Trang Le Dinh Dang, Dongkyu Seo, Jin-Woo Han, Jinsang Kim, Ik-Joon Chang
2018	—	`conf`	A Radiation Hardened SRAM with Self-refresh and Compact Error Correction. ISOCC M. Sultan M. Siddiqui, Ruchi Sharma, Van Loi Le, Taegeun Yoo, Ik-Joon Chang, Tony Tae-Hyoung Kim
2016	J	`jnl`	0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization. IEEE J. Solid State Circuits Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Xin Liu, Tony Tae-Hyoung Kim
2014	—	`conf`	0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. A-SSCC Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Tony Tae-Hyoung Kim
2006	J	`jnl`	PVT-aware leakage reduction for on-die caches with improved read stability. IEEE J. Solid State Circuits Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy