Igor Loi

61 papers A 11C 4Journal 26Unranked 20
YearRankTypeTitle / Venue / Authors
2023 J jnl
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters.
CoRR
Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2023 J jnl
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters.
IEEE Trans. Very Large Scale Integr. Syst.
Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2022 J jnl
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021 — conf
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
ISSCC
Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021 J jnl
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2020 A conf
Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster.
DATE
Jie Chen, Igor Loi, Luca Benini, Davide Rossi
2019 J jnl
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing.
IEEE J. Solid State Circuits
Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
2018 J jnl
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2018 — conf
GAP-8: A RISC-V SoC for AI at the Edge of the IoT.
ASAP
Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini
2018 — conf
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing.
ESSCIRC
Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini
2018 J jnl
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
IEEE Trans. Parallel Distributed Syst.
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2018 C conf
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
ISCAS
Martino Dazzi, Pierpaolo Palestri, Davide Rossi, Andrea Bandiziol, Igor Loi, David E. Bellasi, Luca Benini
2018 J jnl
The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores.
IEEE Trans. Multi Scale Comput. Syst.
Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
2017 J jnl
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters.
IEEE Embed. Syst. Lett.
Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini
2017 J jnl
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test
Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
2017 J jnl
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2017 J jnl
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017 J jnl
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.
IEEE Trans. Very Large Scale Integr. Syst.
Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini
2017 J jnl
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. Very Large Scale Integr. Syst.
Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2017 J jnl
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
CoRR
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2016 — conf
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
COOL Chips
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016 C conf
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
ISCAS
Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2016 — conf
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
ReConFig
Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
2016 J jnl
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices.
CoRR
Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2016 J jnl
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
CoRR
Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2016 — conf
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.
Conf. Computing Frontiers
Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
2016 — conf
Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.
ARCS
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2016 J jnl
On-the-fly adaptivity for process networks over shared-memory platforms.
Microprocess. Microsystems
Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo, Giovanni Pietro Seu, Igor Loi, Francesco Conti, Luigi Raffo
2016 J jnl
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
J. Signal Process. Syst.
Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2015 J jnl
A Modular Shared L2 Memory Design for 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst.
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2015 — conf
Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.
Conf. Computing Frontiers
Igor Loi, Davide Rossi, Germain Haugou, Michael Gautschi, Luca Benini
2015 A conf
High performance AXI-4.0 based interconnect for extensible smart memory cubes.
DATE
Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
2015 — conf
PULP: A parallel ultra low power platform for next generation IoT applications.
Hot Chips Symposium
Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
2014 — conf
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
MES
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
2014 A conf
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms.
DATE
Igor Loi, Luca Benini
2014 — conf
Energy-efficient vision on the PULP platform for ultra-low power parallel computing.
SiPS
Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2014 — conf
Online process transformation for polyhedral process networks in shared-memory MPSoCs.
MECO
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
2014 — conf
Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters.
Conf. Computing Frontiers
Davide Rossi, Igor Loi, Germain Haugou, Luca Benini
2013 — conf
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.
NOCS
Erfan Azarkhish, Igor Loi, Luca Benini
2013 J jnl
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects.
IET Comput. Digit. Tech.
Erfan Azarkhish, Igor Loi, Luca Benini
2013 — conf
A high-performance multiported L2 memory IP for scalable three-dimensional integration.
3DIC
Erfan Azarkhish, Igor Loi, Luca Benini
2013 — conf
A shared-FPU architecture for ultra-low power MPSoCs.
Conf. Computing Frontiers
Mohammad Reza Kakoee, Igor Loi, Luca Benini
2013 J jnl
Exploration and Optimization of 3-D Integrated DRAM Subsystems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Christian Weis, Igor Loi, Luca Benini, Norbert Wehn
2012 C conf
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.
VLSI-SoC
Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
2012 A conf
A resilient architecture for low latency communication in shared-L1 processor clusters.
DATE
Mohammad Reza Kakoee, Igor Loi, Luca Benini
2012 A conf
An energy efficient DRAM subsystem for 3D integrated SoCs.
DATE
Christian Weis, Igor Loi, Luca Benini, Norbert Wehn
2012 — conf
Configurable Low-Latency Interconnect for Multi-core Clusters.
VLSI-SoC (Selected Papers)
Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
2012 J jnl
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters.
IEEE Trans. Circuits Syst. II Express Briefs
Mohammad Reza Kakoee, Igor Loi, Luca Benini
2011 A conf
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.
DATE
Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini
2011 J jnl
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini
2011 J jnl
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits
Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
2011 A conf
Design space exploration for 3D-stacked DRAMs.
DATE
Christian Weis, Norbert Wehn, Igor Loi, Luca Benini
2011 — conf
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.
PATMOS
Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini
2010 C conf
3D NoCs - Unifying inter & intra chip communication.
ISCAS
Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini
2010 — conf
A new physical routing approach for robust bundled signaling on NoC links.
ACM Great Lakes Symposium on VLSI
Mohammad Reza Kakoee, Igor Loi, Luca Benini
2010 A conf
An efficient distributed memory interface for many-core platform with 3D stacked DRAM.
DATE
Igor Loi, Luca Benini
2009 A conf
Synthesis of low-overhead configurable source routing tables for network interfaces.
DATE
Igor Loi, Federico Angiolini, Luca Benini
2008 A conf
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
ICCAD
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini
2008 A conf
Developing Mesochronous Synchronizers to Enable 3D NoCs.
DATE
Igor Loi, Federico Angiolini, Luca Benini
2007 J jnl
Area and Power Modeling for Networks-on-Chip with Layout Awareness.
VLSI Design
Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini
2007 — conf
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow.
Nano-Net
Igor Loi, Federico Angiolini, Luca Benini