Igor Aleksejev

11 papers A 2B 2Journal 2Unranked 5
YearRankTypeTitle / Venue / Authors
2017 J jnl
Run-time reconfigurable instruments for advanced board-level testing.
IEEE Instrum. Meas. Mag.
Igor Aleksejev, Artur Jutman, Sergei Devadze
2016 B conf
On coverage of timing related faults at board level.
ETS
Artur Jutman, Igor Aleksejev, Sergei Devadze
2016 J jnl
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures.
J. Electron. Test.
Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
2015 — conf
Complex delay fault reasoning with sequential 7-valued algebra.
LATS
Jaak Kousaar, Raimund Ubar, Igor Aleksejev
2015 — conf
Virtual reconfigurable scan-chains on FPGAs for optimized board test.
LATS
Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
2012 B conf
Embedded synthetic instruments for Board-Level testing.
ETS
Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel
2012 A conf
FPGA-based synthetic instrumentation for board test.
ITC
Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel
2011 — conf
Invited paper: System-wide fault management based on IEEE P1687 IJTAG.
ReCoSoC
Artur Jutman, Sergei Devadze, Igor Aleksejev
2009 A conf
Fast extended test access via JTAG and FPGAs.
ITC
Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2009 — conf
Turning JTAG inside out for fast extended test access.
LATW
Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2008 — conf
Reseeding using compaction of pre-generated LFSR sub-sequences.
ICECS
Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar