Ignacio Algredo-Badillo

32 papers C 1Journal 23Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Biometric lock with facial recognition implemented with deep learning techniques. Comput. Sci. Inf. Syst. José Misael Burruel-Zazueta, Héctor Rodríguez Rangel, Gloria Ekaterine Peralta-Peñuñuri, Vicenç Puig Cayuela, Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales
2023	—	`conf`	White-Box Adversarial Attacks Against Sentiment-Analysis Models using an Aspect-Based Approach. CISETC Monserrat Vázquez-Hernández, Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales, Luis Villaseñor-Pineda
2022	J	`jnl`	A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. Sensors Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Mariana Lobato Báez, Luis Alberto Morales-Rosales
2022	J	`jnl`	An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy. Sensors Alan Torres-Alvarado, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel
2022	J	`jnl`	Irregularities recognition system for automotive pieces. Int. J. Comput. Vis. Robotics Ignacio Algredo-Badillo, Germàn Portillo-García, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales
2022	J	`jnl`	Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models. Sensors Alan Torres-Alvarado, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel
2021	J	`jnl`	A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo
2021	J	`jnl`	Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools. J. Circuits Syst. Comput. Daniel Pacheco Bautista, Ricardo Carreño Aguilera, Francisco Aguilar Acevedo, Ignacio Algredo-Badillo
2021	J	`jnl`	CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions. Sensors Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Monica Amador García, Jorge Antonio Orozco Torres
2021	J	`jnl`	Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES. Sensors Ignacio Algredo-Badillo, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales, Daniel Pacheco Bautista, Claudia Feregrino-Uribe
2020	J	`jnl`	A Metaheuristic Optimization Approach for Parameter Estimation in Arrhythmia Classification from Unbalanced Data. Sensors Juan Carlos Carrillo-Alarcón, Luis Alberto Morales-Rosales, Héctor Rodríguez Rangel, Mariana Lobato Báez, Antonio Muñoz, Ignacio Algredo-Badillo
2020	J	`jnl`	A fuzzy petri net model for assessing analogical reasoning in children ranging from 5 to 8 years old. J. Intell. Fuzzy Syst. Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Mariana Lobato Báez, Carlos Arturo Hernández-Gracidas, Héctor Rodríguez Rangel
2019	J	`jnl`	Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety. J. Intell. Fuzzy Syst. Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales, Carlos Arturo Hernández-Gracidas, Juan C. Cruz-Victoria, Daniel Pacheco Bautista, Miguel Morales-Sandoval
2019	J	`jnl`	Reconfigurable arithmetic logic unit designed with threshold logic gates. IET Circuits Devices Syst. Alejandro Medina-Santiago, Mario Alfredo Reyes-Barranca, Ignacio Algredo-Badillo, Alfonso Martinez Cruz, Kelsey A. Ramírez-Gutiérrez, Eleazar Adrián Cortés-Barrón
2018	J	`jnl`	Lightweight Security Hardware Architecture Using DWT and AES Algorithms. IEICE Trans. Inf. Syst. Ignacio Algredo-Badillo, Francisco Rubén Castillo Soria, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales, Alejandro Medina-Santiago, Claudia Feregrino-Uribe
2018	J	`jnl`	On-road obstacle detection video system for traffic accident prevention. J. Intell. Fuzzy Syst. Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Carlos Arturo Hernández-Gracidas, Héctor Rodríguez Rangel, Mariana Lobato Báez
2017	—	`conf`	A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS Luis Armando Rodriguez Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo-Badillo
2015	—	`conf`	A comparative study of the wavenet PID controllers for applications in non-linear systems. CCE M. A. Saldaña-O., Luis Enrique Ramos-Velasco, J. P. Ordaz-O., Abel García-Barrientos, Ignacio Algredo-Badillo, Jean-François Balmat, Frédéric Lafont
2014	J	`jnl`	A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido
2013	—	`conf`	A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo-Badillo
2013	J	`jnl`	FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2012	J	`jnl`	A Lossless Data Hiding Technique based on AES-DWT CoRR Francisco Rubén Castillo Soria, Gustavo Fernández Torres, Ignacio Algredo-Badillo
2012	J	`jnl`	Performance Analysis of ANFIS in short term Wind Speed Prediction CoRR Ernesto Cortés Pérez, Ignacio Algredo-Badillo, Víctor Hugo García Rodríguez
2012	—	`conf`	Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido
2011	C	`conf`	Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2010	J	`jnl`	A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo
2010	J	`jnl`	Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2009	—	`conf`	A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo
2009	J	`jnl`	An area/performance trade-off analysis of a GF(2 Comput. Electr. Eng. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo
2008	J	`jnl`	Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2008	—	`conf`	FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2006	—	`conf`	Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido