Ibrahim N. Hajj

101 papers A* 9A 22C 10Misc 7Journal 27Unranked 26
YearRankTypeTitle / Venue / Authors
2017 C conf
Beyond SPICE.
ISCAS
Ibrahim N. Hajj
2015 J jnl
On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ibrahim N. Hajj
2012 J jnl
Extended Nodal Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ibrahim N. Hajj
2004 J jnl
Postroute gate sizing for crosstalk noise reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2003 J jnl
Early probabilistic noise estimation for capacitively coupled interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
2003 — conf
Post-Route Gate Sizing for Crosstalk Noise Reduction.
ISQED
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2003 A* conf
Post-route gate sizing for crosstalk noise reduction.
DAC
Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2002 J jnl
A technique for Improving dual-output domino logic.
IEEE Trans. Very Large Scale Integr. Syst.
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
2002 A conf
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .
DATE
Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
2002 — conf
Early probabilistic noise estimation for capacitively coupled interconnects.
SLIP
Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda
2002 J jnl
Estimation of state line statistics in sequential circuits.
ACM Trans. Design Autom. Electr. Syst.
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
2002 — conf
Pre-route Noise Estimation in Deep Submicron Integrated Circuits.
ISQED
Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj
2002 — conf
Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network.
ISQED
Geng Bai, Ibrahim N. Hajj
2001 — conf
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model.
ISQED
Ninglong Lu, Ibrahim N. Hajj
2001 — conf
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
ISQED
Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
2001 — conf
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.
ISCAS (5)
Sudhakar Bobba, Ibrahim N. Hajj
2001 — conf
Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms.
ICECS
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
2001 A conf
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models.
ISLPED
Sudhakar Bobba, Ibrahim N. Hajj
2001 — conf
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
ISQED
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
2001 — conf
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
ISQED
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
2001 A* conf
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits.
DAC
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
2000 — conf
A hierarchical based approach for coupling aware delay analysis of combinational logic blocks.
ICECS
Ninglong Lu, Ibrahim N. Hajj
2000 — conf
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling.
ISQED
Murat R. Becer, Ibrahim N. Hajj
2000 — conf
An analytical model for delay and crosstalk estimation in interconnects under general switching conditions.
ICECS
Murat R. Becer, Ibrahim N. Hajj
2000 J jnl
Architectural and compiler techniques for energy reduction in high-performance microprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George I. Stamoulis
2000 C conf
Current-Mode Threshold Logic Gates.
ICCD
Sudhakar Bobba, Ibrahim N. Hajj
2000 — conf
High-performance bidirectional repeaters.
ACM Great Lakes Symposium on VLSI
Sudhakar Bobba, Ibrahim N. Hajj
2000 — conf
Instruction scheduling for low power on dynamically variable voltage processors.
ICECS
Mohammad M. Mansour, Makram M. Mansour, Ibrahim N. Hajj, Naresh R. Shanbhag
2000 Misc conf
Peak current estimation for digital filters.
ICASSP
Sudhakar Bobba, Ibrahim N. Hajj
2000 — conf
Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
ISQED
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
2000 A conf
Simulation and Optimization of the Power Distribution Network in VLSI Circuits.
ICCAD
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
2000 J jnl
Using dynamic cache management techniques to reduce energy in general purpose processors.
IEEE Trans. Very Large Scale Integr. Syst.
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
1999 J jnl
A coding framework for low-power address and data busses.
IEEE Trans. Very Large Scale Integr. Syst.
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1999 — conf
A hybrid approach to design error detection and correction [VLSI digital circuits].
ICECS
Andreas G. Veneris, Ibrahim N. Hajj
1999 — conf
A reduced-order scheme for coupled lumped-distributed interconnect simulation.
ISCAS (6)
Ninglong Lu, Ibrahim N. Hajj
1999 — conf
An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications.
Great Lakes Symposium on VLSI
Ninglong Lu, Ibrahim N. Hajj
1999 — conf
An analytical, transistor-level energy model for SRAM-based caches.
ISCAS (6)
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
1999 A conf
An optimization technique for dual-output domino logic.
ISLPED
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
1999 Misc conf
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.
VLSI Design
Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag
1999 — conf
Correcting multiple design errors in digital VLSI circuits.
ISCAS (1)
Andreas G. Veneris, Ibrahim N. Hajj
1999 J jnl
Design error diagnosis and correction via test vector simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andreas G. Veneris, Ibrahim N. Hajj
1999 C conf
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.
ICCD
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis
1999 J jnl
Information-theoretic bounds on average signal transition activity [VLSI systems].
IEEE Trans. Very Large Scale Integr. Syst.
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1999 — conf
Low-power distributed arithmetic architectures using nonuniform memory partitioning.
ISCAS (3)
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1999 Misc conf
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.
VTS
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs
1999 A conf
Using dynamic cache management techniques to reduce energy in a high-performance processor.
ISLPED
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
1998 A conf
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
ISLPED
Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos
1998 Misc conf
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.
VLSI Design
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1998 A conf
Decorrelating (DECOR) transformations for low-power adaptive filters.
ISLPED
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1998 — conf
Estimation of maximum current envelope for power bus analysis and design.
ISPD
Sudhakar Bobba, Ibrahim N. Hajj
1998 — conf
Maximum Current Estimation in Programmable Logic Arrays.
Great Lakes Symposium on VLSI
Sudhakar Bobba, Ibrahim N. Hajj
1997 — conf
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.
Great Lakes Symposium on VLSI
Andreas G. Veneris, Ibrahim N. Hajj
1997 A conf
Achievable bounds on signal transition activity.
ICCAD
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1997 A* conf
Analytical Estimation of Transition Activity From Word-Level Signal Statistics.
DAC
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1997 J jnl
Analytical estimation of signal transition activity from word-level statistics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
1997 J jnl
Diagnosis and correction of multiple logic design errors in digital circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Pi-Yu Chung, Ibrahim N. Hajj
1997 A conf
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.
ICCAD
Tzuhao Chen, Ibrahim N. Hajj
1997 — conf
Monte-Carlo approach for power estimation in sequential circuits.
ED&TC
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
1996 J jnl
Computer-aided redesign of VLSI circuits for hot-carrier reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ping-Chung Li, Ibrahim N. Hajj
1996 Misc conf
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
VTS
Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
1995 J jnl
Circuit-level dictionaries of CMOS bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs
1995 J jnl
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
1995 A* conf
Power Estimation in Sequential Circuits.
DAC
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
1995 J jnl
Timing and area optimization for standard-cell VLSI circuit design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
1994 J jnl
A probabilistic timing approach to hot-carrier effect estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
1994 Misc conf
Circuit-level dictionaries of CMOS bridging faults.
VTS
Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs
1994 A conf
Delay and area optimization for compact placement by gate resizing and relocation.
ICCAD
Weitong Chuang, Ibrahim N. Hajj
1994 C conf
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
ISCAS
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
1994 J jnl
Logic design error diagnosis and correction.
IEEE Trans. Very Large Scale Integr. Syst.
Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
1993 A conf
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
ICCAD
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
1993 C conf
Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability.
ICCD
Ping-Chung Li, Ibrahim N. Hajj
1993 A* conf
Diagnosis and Correction of Logic Design Errors in Digital Circuits.
DAC
Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
1993 C conf
Efficient Variable Ordering Heuristics for Shared ROBDD.
ISCAS
Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel
1993 C conf
Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection.
ISCAS
Weitong Chuang, Ibrahim N. Hajj
1993 A* conf
Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects.
DAC
Georgios I. Stamoulis, Ibrahim N. Hajj
1993 A* conf
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
DAC
Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj
1993 J jnl
Switch-level timing simulation of bipolar ECL circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj
1992 A conf
A probabilistic timing approach to hot-carrier effect estimation.
ICCAD
Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
1992 A conf
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits.
ITC
Pi-Yu Chung, Ibrahim N. Hajj
1992 A* conf
Maximum Current Estimation in CMOS Circuits.
DAC
Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
1992 Misc conf
Simulation of physical faults in VLSI circuits.
VTS
Ibrahim N. Hajj, Terry Lee
1991 A conf
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation.
ICCAD
Terry Lee, Ibrahim N. Hajj
1991 J jnl
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
1990 J jnl
A metal - metal matrix cell generator for multi-level metal MOS technology.
Integr.
P. Gee, Min-You Wu, S. M. Kang, Ibrahim N. Hajj
1990 J jnl
A multilevel parallel solver for block tridiagonal and banded linear systems.
Parallel Comput.
Ibrahim N. Hajj, Stig Skelboe
1990 A conf
An Algebra for Switch-Level Simulation.
ICCAD
Ibrahim N. Hajj
1990 C conf
High speed VLSI logic simulation using bitwise operations and parallel processing.
ICCD
Young-Hyun Jun, Ibrahim N. Hajj, Sang-Heon Lee, Song-Bai Park
1990 J jnl
Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
1990 J jnl
The complexity of fault detection in MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farid N. Najm, Ibrahim N. Hajj
1989 A conf
A custom cell generation system for double-metal CMOS technology.
ICCAD
P. Gee, Ibrahim N. Hajj, Sung-Mo Kang
1989 A conf
Automatic mixed-mode timing simulation.
ICCAD
David Overhauser, Ibrahim N. Hajj, Yi-Fan Hsu
1989 A conf
Computation of bus current variance for reliability estimation of VLSI circuits.
ICCAD
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
1989 C conf
Electromigration median time-to-failure based on a stochastic current waveform.
ICCD
Farid N. Najm, Ibrahim N. Hajj, Ping Yang
1989 C conf
Parallel-concurrent fault simulation.
ICCD
Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh
1989 J jnl
Switching network logic approach to sequential MOS circuit design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Min-You Wu, Ibrahim N. Hajj
1988 A conf
A tabular macromodeling approach to fast timing simulation including parasitics.
ICCAD
David Overhauser, Ibrahim N. Hajj
1988 A conf
CREST-a current estimator for CMOS circuits.
ICCAD
Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
1988 A* conf
Delay Modeling and Time of Bipolar Digital Circuits.
DAC
Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj
1988 A conf
iEDISON: an interactive statistical design tool for MOS VLSI circuits.
ICCAD
Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick
1988 A conf
iPRIDE: a parallel integrated circuit simulator using direct method.
ICCAD
Mi-Chang Chang, Ibrahim N. Hajj
1987 J jnl
Switch-Level Logic Simulation of Digital Bipolar Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ibrahim N. Hajj, Daniel G. Saab