Ibrahim Hur

46 papers A* 7A 1B 10Misc 1Journal 19Unranked 8
YearRankTypeTitle / Venue / Authors
2024 J jnl
Accurate and Scalable Many-Node Simulation.
CoRR
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2024 A* conf
HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures.
HPCA
Gerasimos Gerogiannis, Sriram Aananthakrishnan, Josep Torrellas, Ibrahim Hur
2023 B conf
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation.
ISPASS
Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur
2023 J jnl
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor.
IEEE Micro
Sriram Aananthakrishnan, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche
2022 B conf
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks.
ISPASS
Stijn Eyerman, Wim Heirman, Ibrahim Hur
2022 J jnl
Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study.
CoRR
Stijn Eyerman, Ibrahim Hur
2022 — conf
Towards a GraphBLAS Implementation for Go.
IPDPS Workshops
Pascal Costanza, Ibrahim Hur, Timothy G. Mattson
2021 J jnl
Automatic Sublining for Efficient Sparse Memory Accesses.
ACM Trans. Archit. Code Optim.
Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
2021 A* conf
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions.
MICRO
Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
2021 J jnl
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model.
IEEE Comput. Archit. Lett.
Stijn Eyerman, Wim Heirman, Ibrahim Hur
2021 J jnl
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors.
IEEE Comput. Archit. Lett.
Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
2020 J jnl
Breaking In-Order Branch Miss Recovery.
IEEE Comput. Archit. Lett.
Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
2020 — conf
Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture.
HPEC
Sriram Aananthakrishnan, Robert Pawlowski, Joshua B. Fryman, Ibrahim Hur
2020 — conf
Hash Table Scalability on Intel PIUMA.
HPEC
Balasubramanian Seshasayee, Joshua B. Fryman, Ibrahim Hur
2020 J jnl
PIUMA: Programmable Integrated Unified Memory Architecture.
CoRR
Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz
2020 — conf
Projecting Performance for PIUMA using Down-Scaled Simulation.
HPEC
Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur
2018 B conf
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks.
ISPASS
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2018 A conf
Many-core graph workload analysis.
SC
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur
2018 J jnl
Multi-Stage CPI Stacks.
IEEE Comput. Archit. Lett.
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2018 B conf
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors.
PACT
Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur
2017 — conf
Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms.
HPEC
Ancy Sarah Tom, Narayanan Sundaram, Nesreen K. Ahmed, Shaden Smith, Stijn Eyerman, Midhunchandra Kodiyath, Ibrahim Hur, Fabrizio Petrini, George Karypis
2015 J jnl
Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code.
Concurr. Comput. Pract. Exp.
A. Vapirev, Jan Deca, Giovanni Lapenta, Stefano Markidis, Ibrahim Hur, Jean-Luc Cambier
2014 J jnl
An Evaluation of High-Level Mechanistic Core Models.
ACM Trans. Archit. Code Optim.
Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout
2014 — conf
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor.
ROSS@ICS
Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
2014 A* conf
Undersubscribed threading on clustered cache architectures.
HPCA
Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
2012 J jnl
Circuit design of a dual-versioning L1 data cache.
Integr.
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012 J jnl
Hardware transactional memory with software-defined conflicts.
ACM Trans. Archit. Code Optim.
J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012 B conf
Power-aware multi-core simulation for early design stage hardware/software co-optimization.
PACT
Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout
2012 J jnl
Profiling and Optimizing Transactional Memory Applications.
Int. J. Parallel Program.
Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2012 J jnl
Resource-bounded multicore emulation using Beefarm.
Microprocess. Microsystems
Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 — conf
Circuit design of a dual-versioning L1 data cache for optimistic concurrency.
ACM Great Lakes Symposium on VLSI
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2011 — conf
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.
ARC
Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero
2011 J jnl
RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).
SIGMETRICS Perform. Evaluation Rev.
Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 B conf
RMS-TM: a comprehensive benchmark suite for transactional memory systems.
ICPE
Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 B conf
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.
PACT
Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 B conf
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
PACT
Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2011 Misc conf
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.
FCCM
Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero
2011 B conf
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
PACT
Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero
2010 B conf
Discovering and understanding performance bottlenecks in transactional applications.
PACT
Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero
2010 J jnl
The Velox Transactional Memory Stack.
IEEE Micro
Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Rivière, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel
2009 A* conf
Feedback mechanisms for improving probabilistic memory prefetching.
HPCA
Ibrahim Hur, Calvin Lin
2008 A* conf
A comprehensive approach to DRAM power management.
HPCA
Ibrahim Hur, Calvin Lin
2007 J jnl
Memory scheduling for modern microprocessors.
ACM Trans. Comput. Syst.
Ibrahim Hur, Calvin Lin
2006 J jnl
Adaptive History-Based Memory Schedulers for Modern Processors.
IEEE Micro
Ibrahim Hur, Calvin Lin
2006 A* conf
Memory Prefetching Using Adaptive Stream Detection.
MICRO
Ibrahim Hur, Calvin Lin
2004 A* conf
Adaptive History-Based Memory Schedulers.
MICRO
Ibrahim Hur, Calvin Lin