Ian Galton

87 papers C 5Misc 1Journal 58Unranked 23
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 2.5-20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery.
IEEE J. Solid State Circuits
Aditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Asish Koruprolu, Corentin Pochet, Andrew M. Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall
2025 — conf
A Scalable 256-Channel 12-mA 0.06%-Current-Mismatch 22-V Neurostimulator with Real-Time Current Calibration and Compliance Monitoring.
CICC
Po-Han Chen, Zhiheng Luo, Spencer Chang, Kristopher Ngo, Ritwik Vatsyayan, Jihwan Lee, Tara Porter, Drew A. Hall, Shadi A. Dayeh, Ian Galton, Hanh-Phuc Le
2025 J jnl
Enhanced ISI Analysis and Fast Circuit Simulation of High-Speed Current-Steering DACs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Subin Kim, Ian Galton
2024 — conf
A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording.
CICC
Aditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Corentin Pochet, Andrew M. Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall
2024 J jnl
A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amr I. Eissa, Enrique Alvarez-Fontecilla, Colin Weltin-Wu, Ian Galton
2023 J jnl
Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Subin Kim, Ian Galton
2022 J jnl
An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs.
IEEE J. Solid State Circuits
Jason Remple, Andrea Panigada, Ian Galton
2022 J jnl
DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Eslam Helal, Amr I. Eissa, Ian Galton
2021 J jnl
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL.
IEEE J. Solid State Circuits
Eslam Helal, Enrique Alvarez-Fontecilla, Amr I. Eissa, Ian Galton
2021 J jnl
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton
2021 J jnl
Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs.
IEEE J. Solid State Circuits
Enrique Alvarez-Fontecilla, Eslam Helal, Amr I. Eissa, Ian Galton
2020 J jnl
MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Derui Kong, Ian Galton
2019 — conf
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
VLSI Circuits
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
2019 J jnl
A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error.
IEEE J. Solid State Circuits
Derui Kong, Kevin Rivas-Rivera, Ian Galton
2019 J jnl
Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Derui Kong, Ian Galton
2019 J jnl
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ian Galton, Colin Weltin-Wu
2018 J jnl
Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Derui Kong, Ian Galton
2018 J jnl
Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Enrique Alvarez-Fontecilla, Christian Venerus, Ian Galton
2017 — conf
Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs.
CICC
Eythan Familier, Ian Galton
2017 J jnl
The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jason Remple, Ian Galton
2016 J jnl
Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Eythan Familier, Ian Galton
2016 J jnl
Simplified Logic for Tree-Structure Segmented DEM Encoders.
IEEE Trans. Circuits Syst. II Express Briefs
Christian Venerus, Jason Remple, Ian Galton
2015 — conf
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation.
ISSCC
Colin Weltin-Wu, Guobi Zhao, Ian Galton
2015 J jnl
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion.
IEEE J. Solid State Circuits
Colin Weltin-Wu, Guobi Zhao, Ian Galton
2015 J jnl
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Colin Weltin-Wu, Eythan Familier, Ian Galton
2015 J jnl
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO.
IEEE J. Solid State Circuits
Christian Venerus, Ian Galton
2015 J jnl
Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO".
IEEE J. Solid State Circuits
Christian Venerus, Ian Galton
2015 J jnl
Quantization Noise Cancellation for FDC-Based Fractional-N PLLs.
IEEE Trans. Circuits Syst. II Express Briefs
Christian Venerus, Ian Galton
2013 J jnl
A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones.
IEEE Trans. Signal Process.
Eythan Familier, Christian Venerus, Ian Galton
2013 J jnl
A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones.
IEEE Trans. Signal Process.
Eythan Familier, Ian Galton
2013 J jnl
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB.
IEEE J. Solid State Circuits
Gerry Taylor, Ian Galton
2013 J jnl
Delta-Sigma FDC Based Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Christian Venerus, Ian Galton
2013 J jnl
Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nevena Rakuljic, Ian Galton
2012 — conf
A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB.
VLSIC
Gerry Taylor, Ian Galton
2011 J jnl
A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kevin J. Wang, Ian Galton
2011 J jnl
Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261].
IEEE J. Solid State Circuits
Gerry Taylor, Ian Galton
2010 J jnl
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC.
IEEE J. Solid State Circuits
Gerry Taylor, Ian Galton
2010 — conf
A mostly digital variable-rate continuous-time ADC ΔΣ modulator.
ISSCC
Gerry Taylor, Ian Galton
2010 — conf
CMOS phase-locked loops for frequency synthesis.
ISSCC
Ian Galton, Behzad Razavi, John Cowles, Peter R. Kinget
2010 J jnl
Tree-Structured DEM DACs with Arbitrary Numbers of Levels.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nevena Rakuljic, Ian Galton
2010 J jnl
Why Dynamic-Element-Matching DACs Work.
IEEE Trans. Circuits Syst. II Express Briefs
Ian Galton
2009 J jnl
A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction.
IEEE J. Solid State Circuits
Andrea Panigada, Ian Galton
2009 — conf
A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction.
ISSCC
Andrea Panigada, Ian Galton
2009 — conf
Low-voltage analog and mixed-signal CMOS circuit design.
ISSCC
Ian Galton
2008 J jnl
Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs.
IEEE J. Solid State Circuits
Kok Lim Chan, Jianyu Zhu, Ian Galton
2008 J jnl
Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kok Lim Chan, Nevena Rakuljic, Ian Galton
2008 — conf
Short Course.
ISSCC
Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders
2008 — conf
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL.
ISSCC
Kevin J. Wang, Ashok Swaminathan, Ian Galton
2008 J jnl
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL.
IEEE J. Solid State Circuits
Kevin J. Wang, Ashok Swaminathan, Ian Galton
2007 J jnl
A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion.
IEEE Trans. Signal Process.
Ashok Swaminathan, Andrea Panigada, Elias Masry, Ian Galton
2007 J jnl
A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation.
IEEE J. Solid State Circuits
Ashok Swaminathan, Kevin J. Wang, Ian Galton
2007 — conf
A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation.
ISSCC
Ashok Swaminathan, Kevin J. Wang, Ian Galton
2007 — conf
Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS.
ISSCC
Ian Galton, Matt Miller, Robert Bogdan Staszewski, Bram Nauta, Michiel Steyaert
2007 J jnl
LSB Dithering in MASH Delta-Sigma D/A Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sudhakar Pamarti, Ian Galton
2007 J jnl
Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sudhakar Pamarti, Jared Welz, Ian Galton
2006 — conf
A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching.
ISSCC
Kok Lim Chan, Ian Galton
2006 J jnl
Digital Background Correction of Harmonic Distortion in Pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Panigada, Ian Galton
2005 J jnl
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation".
IEEE J. Solid State Circuits
Sudhakar Pamarti, Lars C. Jansson, Ian Galton
2004 J jnl
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC.
IEEE J. Solid State Circuits
Eric Siragusa, Ian Galton
2004 J jnl
A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter.
IEEE Trans. Inf. Theory
Jared Welz, Ian Galton
2004 J jnl
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation.
IEEE J. Solid State Circuits
Sudhakar Pamarti, Lars C. Jansson, Ian Galton
2004 J jnl
Techniques for phase noise suppression in recirculating DLLs.
IEEE J. Solid State Circuits
Sheng Ye, Ian Galton
2003 J jnl
Editorial.
IEEE Trans. Circuits Syst. II Express Briefs
Ian Galton
2003 J jnl
Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs.
IEEE Trans. Circuits Syst. II Express Briefs
Sudhakar Pamarti, Ian Galton
2003 — conf
Techniques for in-band phase noise suppression in re-circulating DLLs.
CICC
Sheng Ye, Lars C. Jansson, Ian Galton
2002 J jnl
A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver.
IEEE J. Solid State Circuits
Jorge Grilo, Ian Galton, Kevin J. Wang, Raymond Montemayor
2002 J jnl
A multiple-crystal interface PLL with VCO realignment to reduce phase noise.
IEEE J. Solid State Circuits
Sheng Ye, Lars C. Jansson, Ian Galton
2002 — conf
A necessary and sufficient condition for mismatch shaping in multi-bit DACs.
ISCAS (1)
Jared Welz, Ian Galton
2002 — conf
Segmented mismatch-shaping D/A conversion.
ISCAS (4)
Asaf Fishov, Eric Siragusa, Jared Welz, Eric Fogleman, Ian Galton
2001 — conf
A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver.
CICC
Jorge Grilo, Ian Galton, Kevin Wang, Raymond Montemayor
2001 J jnl
An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC.
IEEE J. Solid State Circuits
Eric Fogleman, Jared Welz, Ian Galton
2001 Misc conf
The mismatch-noise PSD from a tree-structured DAC in a second-order ΔΣ modulator with a midscale input.
ICASSP
Jared Welz, Ian Galton
2000 J jnl
A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR.
IEEE J. Solid State Circuits
Eric Fogleman, Ian Galton, William Huff, Henrik Jensen
2000 — conf
An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC.
CICC
Eric Fogleman, Jared Welz, Ian Galton
1999 — conf
A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD.
CICC
Eric Fogleman, Ian Galton, William Huff, Henrik Jensen
1999 — conf
A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs.
ISCAS (2)
Eric Fogleman, Ian Galton, Henrik Jensen
1999 — conf
An area-efficient differential input ADC with digital common mode rejection.
ISCAS (2)
Eric Fogleman, Ian Galton, Henrik Jensen
1998 J jnl
A Nyquist-rate delta-sigma A/D converter.
IEEE J. Solid State Circuits
Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez
1998 J jnl
A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal.
IEEE J. Solid State Circuits
Ian Galton, William Huff, Paolo Carbone, Eric Siragusa
1995 C conf
A Practical Second-Order Delta-Digma Frequency-to-Digital Converter.
ISCAS
Ian Galton
1995 C conf
A Robust Parallel Delta-Sigma A/D Converter Architecture.
ISCAS
Henrik T. Jensen, Ian Galton
1994 J jnl
Granular quantization noise in a class of delta-sigma modulators.
IEEE Trans. Inf. Theory
Ian Galton
1994 C conf
Higher-Order Delta-Sigma Frequency to Digital Conversion.
ISCAS
Ian Galton
1993 C conf
Combined RF Phase Extraction and Digitalization.
ISCAS
Ian Galton, George Zimmerman
1993 J jnl
Granular quantization noise in the first-order delta-sigma modulator.
IEEE Trans. Inf. Theory
Ian Galton
1993 C conf
One-bit Dithering in Delta-Sigma Modulator-based D/A Conversion.
ISCAS
Ian Galton
1989 J jnl
An efficient three-point arc algorithm.
IEEE Computer Graphics and Applications
Ian Galton