I-Min Liu

18 papers A* 2A 3C 3Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2010 — conf
Technology mapping with crosstalk noise avoidance.
ASP-DAC
Fang-Yu Fan, Hung-Ming Chen, I-Min Liu
2007 J jnl
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang
2006 J jnl
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
2006 A* conf
Timing-constrained and voltage-island-aware voltage assignment.
DAC
Huaizhi Wu, Martin D. F. Wong, I-Min Liu
2005 A conf
Post-placement voltage island generation under performance requirement.
ICCAD
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang
2005 J jnl
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
2005 — conf
Wire Planning with Bounded Over-the-Block Wires.
ISQED
Hua Xiang, I-Min Liu, Martin D. F. Wong
2004 J jnl
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
2004 C conf
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
ICCD
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
2003 — conf
Floorplanning with power supply noise avoidance.
ASP-DAC
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong
2002 A conf
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.
DATE
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
2001 — conf
Integrated power supply planning and floorplanning.
ASP-DAC
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
2000 C conf
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.
ICCD
I-Min Liu, Adnan Aziz
2000 A conf
Meeting Delay Constraints in DSM by Minimal Repeater Insertion.
DATE
I-Min Liu, Adnan Aziz, D. F. Wong
2000 J jnl
Simultaneous routing and buffer insertion with restrictions onbuffer locations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
2000 — conf
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.
ISPD
I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
1999 C conf
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.
ICCD
I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
1999 A* conf
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.
DAC
Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz