I-Lun Tseng - RankMe

21 papers A* 1C 1Misc 1Journal 8Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Challenges in Floorplanning and Macro Placement for Modern SoCs. ISPD I-Lun Tseng
2024	—	`conf`	Pragmatic EDA Flow Runtime Prediction with Machine Learning and Automatic Outlier Removal. APCCAS I-Lun Tseng
2022	J	`jnl`	Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2022	A*	`conf`	Flexible chip placement via reinforcement learning: late breaking results. DAC Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2019	—	`conf`	A System for Standard Cell Routability Checking and Placement Routability Improvements. APCCAS I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Chun Ming Tommy Yip, Zhinan Chen, Jonathan Ong
2018	J	`jnl`	Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints. CoRR Yongfu Li, Valerio Perez, I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Jason Khaw, Yoong Seang Jonathan Ong
2018	—	`conf`	An Automated System for Checking Lithography Friendliness of Standard Cells. APCCAS I-Lun Tseng, Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong
2018	J	`jnl`	An Automated System for Checking Lithography Friendliness of Standard Cells. CoRR I-Lun Tseng, Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong
2018	J	`jnl`	Context-Aware DFM Rule Analysis and Scoring Using Machine Learning. CoRR Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jonathan Ong
2018	J	`jnl`	Creation and Fixing of Lithography Hotspots with Synopsys Tools. CoRR I-Lun Tseng, Valerio Perez, Yongfu Li, Zhao Chuan Lee, Vikas Tripathi, Yoong Seang Jonathan Ong
2018	—	`conf`	Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching. ISVLSI Yongfu Li, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong
2018	J	`jnl`	In Design DFM Rule Scoring and Fixing Method using ICV. CoRR Vikas Tripathi, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jason Khaw, Jonathan Ong
2013	J	`jnl`	A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons. ACM Trans. Design Autom. Electr. Syst. Yao-Lin Chang, I-Lun Tseng
2013	—	`conf`	Boolean mask operations on parameterized 45-degree polygons. MWSCAS Yao-I Tseng, I-Lun Tseng, Adam Postula
2013	—	`conf`	Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids. NEWCAS Yao-I Tseng, I-Lun Tseng, Tsao Hsiao Huang, Adam Postula
2013	—	`conf`	Relocatable and resizable SRAM synthesis for via configurable structured ASIC. ISQED Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng
2010	Misc	`conf`	Constraint-Based Dogleg Channel Routing with Via Minimization. IC-AI I-Lun Tseng, Huan-Wen Chen, Che-I Lee, Adam Postula
2008	—	`—`	Estimation of Analog Layout Parasitics with Parameterized Polygons I-Lun Tseng
2008	J	`jnl`	Partitioning parameterized 45-degree polygons with constraint programming. ACM Trans. Design Autom. Electr. Syst. I-Lun Tseng, Adam Postula
2006	—	`conf`	An efficient algorithm for partitioning parameterized polygons into rectangles. ACM Great Lakes Symposium on VLSI I-Lun Tseng, Adam Postula
2004	C	`conf`	GBLD: A Formal Model for Layout Description and Generation. FDL I-Lun Tseng, Adam Postula