I-Chyn Wey - RankMe

45 papers C 6Journal 22Unranked 17

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	An Effective Macro Placement Framework with Reinforcement Learning and Monte Carlo Tree Search. ACM Great Lakes Symposium on VLSI Jinghao Ding, Wenxin Yu, Yuanrui Qi, Zhaoqi Fu, Mengshi Gong, I-Chyn Wey, Jinjia Zhou
2024	J	`jnl`	From English to ASIC: Hardware Implementation with Large Language Model. CoRR Emil Goh, Maoyang Xiang, I-Chyn Wey, Tee Hui Teo
2024	J	`jnl`	SF-MMCN: A Low Power Re-configurable Server Flow Convolution Neural Network Accelerator. CoRR Huan-Ke Hsu, I-Chyn Wey, Tee Hui Teo
2023	—	`conf`	A Convolutional Neural Network Inference Accelerator Design using Algorithmic Noise-Tolerance Technology. MCSoC Shih-Yi Yang, I-Chyn Wey, Huan-Ke Hsu, Tee Hui Teo
2023	—	`conf`	A Energy-Efficient Re-configurable Multi-mode Convolution Neuron Network Accelerator. MCSoC Huan-Ke Hsu, I-Chyn Wey, Tee Hui Teo
2023	—	`conf`	Convolutional Neural Networks Inference Accelerator Design using Selective Convolutional Layer. MCSoC Tzu-Huan Huang, I-Chyn Wey, Emil Goh, Tee Hui Teo
2023	J	`jnl`	Design and Verification of a New Universal Active Filter Based on the Current Feedback Operational Amplifier and Commercial AD844 Integrated Circuit. Sensors Hua-Pin Chen, I-Chyn Wey, Liang-Yen Chen, Cheng-Yueh Wu, San-Fu Wang
2023	—	`conf`	Implementation of Physics Informed Neural Networks on Edge Device. MCSoC Xuezhi Zhang, I-Chyn Wey, Maoyang Xiang, Tee Hui Teo
2023	J	`jnl`	Pre-Computing Batch Normalisation Parameters for Edge Devices on a Binarized Neural Network. Sensors Nicholas Phipps, Jin-Jia Shang, Tee Hui Teo, I-Chyn Wey
2023	—	`conf`	Selective Pruning of Sparsity-Supported Energy-Efficient Accelerator for Convolutional Neural Networks. MCSoC Chia-Chi Liu, I-Chyn Wey, Xuezhi Zhang, Tee Hui Teo
2022	—	`conf`	Complex Human Activities Recognition Based on High Performance 1D CNN Model. MCSoC Raman Maurya, Tee Hui Teo, Shi Hui Chua, Hwang-Cherng Chow, I-Chyn Wey
2022	—	`conf`	High-Performance Asynchronous CNN Accelerator with Early Termination. MCSoC Tan Rong Loo, Tee Hui Teo, Mulat Ayinet Tiruye, I-Chyn Wey
2022	—	`conf`	Systolic Array Based Convolutional Neural Network Inference on FPGA. MCSoC Shi Hui Chua, Tee Hui Teo, Mulat Ayinet Tiruye, I-Chyn Wey
2021	C	`conf`	Wearable Parkinson's Disease Finger Tapping Quantitative Evaluation Algorithm Combined with Impedance Sensing. SNPD Jhih-Syong Fong, Ya-Hui Chuang, Fu-Sheng Yu, I-Chyn Wey, San-Fu Wang
2020	J	`jnl`	Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic. IEEE Trans. Circuits Syst. Video Technol. Yufeng Li, Yan Li, I-Chyn Wey, Deqiang Cheng, Fan Yang, Xuan Zeng, Jie Chen
2019	—	`conf`	Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications. ICUFN I-Chyn Wey, Chun-Han Chen, Si-Zhan Fang, Heng-Jui Chou
2018	J	`jnl`	Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method. IEEE J. Solid State Circuits Yan Li, Yufeng Li, I-Chyn Wey, Jianhao Hu, Fan Yang, Xuan Zeng, Xiaoxue Jiang, Jie Chen
2018	J	`jnl`	Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. IEEE Trans. Circuits Syst. I Regul. Pap. Bing-Chen Wu, I-Chyn Wey
2017	J	`jnl`	A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs Xiaojian Yu, Kambiz Moez, I-Chyn Wey, Mohamad Sawan, Jie Chen
2016	J	`jnl`	Fast predictive motion estimation algorithm with adaptive search mode based on motion type classification. Signal Image Video Process. Lili Lin, I-Chyn Wey, Jing-Hua Ding
2016	—	`conf`	Power management design for lab-on-chip biosensors. EMBC Xiaojian Yu, Kambiz Moez, I-Chyn Wey, Jie Chen
2015	J	`jnl`	Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications. IEICE Electron. Express Xin-Xiang Lian, I-Chyn Wey, Chien-Chang Peng, Zhi-Qun Cheng
2015	J	`jnl`	Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique. Int. J. Circuit Theory Appl. I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, Heng-Jui Chou
2015	J	`jnl`	Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. IEEE Trans. Very Large Scale Integr. Syst. I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao
2015	J	`jnl`	Robust C-element design for soft-error mitigation. IEICE Electron. Express I-Chyn Wey, Bing-Chen Wu, Chien-Chang Peng, Cihun-Siyong Alex Gong, Changhong Yu
2014	J	`jnl`	A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. Microelectron. J. I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng
2014	—	`conf`	A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications. GCCE Chun-Yen Wu, Chi-Nan Chuang, Chao-Chyun Chen, I-Chyn Wey
2014	J	`jnl`	All digital folded low-area, low-power maximum power point tracking chip for photovoltaic energy conversion system. Int. J. Circuit Theory Appl. I-Chyn Wey, Shu-Hao Kuo
2014	J	`jnl`	Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits. Integr. I-Chyn Wey, Ye-Jhih Shen
2014	J	`jnl`	Reliable and low error dual modular redundancy FIR filter with wide protection window. IEICE Electron. Express I-Chyn Wey, Chien-Chang Peng, Heng-Jui Chou, Po Tsang Chen
2014	J	`jnl`	Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits. Int. J. Circuit Theory Appl. I-Chyn Wey, Chien-Chang Peng, Hwang-Cherng Chow
2013	J	`jnl`	Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design. Microelectron. Reliab. I-Chyn Wey, Yi-Jung Lan, Chien-Chang Peng
2012	J	`jnl`	Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error. IEEE Trans. Very Large Scale Integr. Syst. I-Chyn Wey, Chun-Chien Wang
2009	J	`jnl`	Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. I-Chyn Wey, You-Gang Chen, Changhong Yu, An-Yeu Wu, Jie Chen
2008	C	`conf`	An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. ISCAS Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu
2008	J	`jnl`	Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. I-Chyn Wey, You-Gang Chen, An-Yeu Wu
2007	—	`conf`	Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. SiPS Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
2007	C	`conf`	Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. ISCAS Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao
2007	C	`conf`	Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ISCAS Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu
2006	C	`conf`	A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. ISCAS Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
2006	C	`conf`	A portable all-digital pulsewidth control loop for SOC applications. ISCAS Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
2005	—	`conf`	A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ISCAS (2) I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu
2005	—	`conf`	A scalable DCO design for portable ADPLL designs. ISCAS (6) Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
2003	—	`conf`	A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. ISCAS (5) Hwang-Cherng Chow, I-Chyn Wey
2002	—	`conf`	A 3.3 V 1 GHz high speed pipelined Booth multiplier. ISCAS (1) Hwang-Cherng Chow, I-Chyn Wey