Héctor Posadas

15 papers C 2Journal 5Unranked 6

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	AI-based estimation of embedded software execution cycles in host-compiled simulation. DCIS Raúl Gómez-Varela, David Aledo, Héctor Posadas, Eugenio Villar
2024	C	`conf`	CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on Video. DSD Daniel Suárez, Víctor Fernández, Héctor Posadas
2023	J	`jnl`	Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards. IEEE Embed. Syst. Lett. Daniel Suárez, Víctor Fernández, Héctor Posadas, Pablo Sánchez
2023	—	`conf`	Automatic code generation from UML for data memory optimization in microcontrollers. DCIS Héctor Posadas, José Luis Vázquez, Eugenio Villar
2023	—	`conf`	UML-Based Design Flow for Systems with Neural Networks. DCIS Daniel Suárez, Héctor Posadas, Víctor Fernández
2020	—	`conf`	Data flow analysis from UML/MARTE models based on binary traces. DCIS Héctor Posadas, Javier Merino, Eugenio Villar
2019	—	`conf`	Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain. DCIS Héctor Posadas, Eugenio Villar, Manuel Sanchez-Renedo
2017	J	`jnl`	Synthesis of simulation and implementation code for OpenMAX multimedia heterogeneous systems from UML/MARTE models. Multim. Tools Appl. David de la Fuente, Jesús Barba, Juan Carlos López, Pablo Peñil, Héctor Posadas, Pablo Sánchez Espeso
2015	J	`jnl`	Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics. J. Syst. Archit. Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar
2014	C	`conf`	Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse. DSD Alejandro Nicolás, Pablo Peñil, Héctor Posadas, Eugenio Villar
2014	J	`jnl`	Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation. Microelectron. J. Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar
2014	J	`jnl`	Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project. Microprocess. Microsystems Héctor Posadas, Alejandro Nicolás, Pablo Peñil, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Mihai T. Lazarescu, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Manuel Prieto
2012	—	`conf`	Automatic synthesis from UML/MARTE models using channel semantics. ACES-MB@MoDELS Pablo Peñil, Héctor Posadas, Alejandro Nicolás, Eugenio Villar
2011	—	`—`	Estimación de prestaciones para exploración de diseño en sistemas embebidos complejos HW/SW ; Early performance estimation for design exploration in complex HW/SW embedded systems. Héctor Posadas
2003	—	`ch.`	Systematic Embedded Software Generation from Systemc. Embedded Software for SoC Fernando Herrera, Héctor Posadas, Pablo Sánchez, Eugenio Villar