Héctor Pettenghi

27 papers B 1C 8Journal 11Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
A Comprehensive Approach and Analysis of Reverse Converters for a Class of Moduli Sets.
LASCAS
Gabriel Fernandes, Augusto Vassoler, Eduardo Bezerra, Leonel Sousa, Héctor Pettenghi
2023 J jnl
RNS processor using moduli sets of the form 2
Int. J. Circuit Theory Appl.
Vanessa Prediger, Fábio Bairros, Laio Oriel Seman, Eduardo Augusto Bezerra, Héctor Pettenghi
2020 J jnl
Towards the Integration of Reverse Converters into the RNS Channels.
IEEE Trans. Computers
Leonel Sousa, Rogerio Paludo, Paulo Martins, Héctor Pettenghi
2019 — conf
Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior.
LASCAS
Fabián Leonardo Cabrera, Fernando Rangel de Sousa, Héctor Pettenghi
2018 J jnl
Efficient RNS Reverse Converters for Moduli Sets with Dynamic Ranges Up to \((10n+1)\) -bit.
Circuits Syst. Signal Process.
Héctor Pettenghi, Rogerio Paludo, Roberto de Matos, Pavel Alekseevich Lyakhov
2017 C conf
Efficient implementation of modular multiplication by constants applied to RNS reverse converters.
ISCAS
Roberto de Matos, Rogerio Paludo, Nikolay I. Chervyakov, Pavel Alekseevich Lyakhov, Héctor Pettenghi
2016 J jnl
Method for designing two levels RNS reverse converters for large dynamic ranges.
Integr.
Héctor Pettenghi, Ricardo Chaves, Roberto de Matos, Leonel Sousa
2016 — conf
RNS reverse converters for moduli sets with dynamic ranges of 9n-bit.
LASCAS
Héctor Pettenghi, Roberto de Matos, Amir Sabbagh Molahosseini
2015 C conf
RNS reverse converters based on the new Chinese Remainder Theorem I.
ISCAS
Héctor Pettenghi, Leonel Sousa
2014 J jnl
Efficient Method for Designing Modulo {2
J. Circuits Syst. Comput.
Héctor Pettenghi, Sorin Cotofana, Leonel Sousa
2014 J jnl
Method for Designing Efficient Mixed Radix Multipliers.
Circuits Syst. Signal Process.
Héctor Pettenghi, Frederico Pratas, Leonel Sousa
2014 C conf
Method for designing multi-channel RNS architectures to prevent power analysis SCA.
ISCAS
Héctor Pettenghi, Jude Angelo Ambrose, Ricardo Chaves, Leonel Sousa
2013 — conf
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks.
ASP-DAC
Jude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa
2013 J jnl
Method to Design General RNS Reverse Converters for Extended Moduli Sets.
IEEE Trans. Circuits Syst. II Express Briefs
Héctor Pettenghi, Ricardo Chaves, Leonel Sousa
2013 J jnl
RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Héctor Pettenghi, Ricardo Chaves, Leonel Sousa
2013 J jnl
Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.
IET Circuits Devices Syst.
Jude Angelo Ambrose, Héctor Pettenghi, Darshana Jayasinghe, Leonel Sousa
2012 — conf
Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion.
ASP-DAC
Héctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose
2012 C conf
RNS Arithmetic Units for Modulo {2^n+-k}.
DSD
Pedro Miguens Matutino, Héctor Pettenghi, Ricardo Chaves, Leonel Sousa
2010 C conf
An improved RNS generator 2
VLSI-SoC
Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo
2009 J jnl
Operation Limits for RTD-Based MOBILE Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi
2008 C conf
A novel contribution to the RTD-based threshold logic family.
ISCAS
Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
2008 J jnl
Using multi-threshold threshold gates in RTD-based logic design: A case study.
Microelectron. J.
Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
2007 C conf
Non Return Mobile Logic Family.
ISCAS
Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
2006 C conf
Self-latching operation limits for MOBILE circuits.
ISCAS
José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
2005 — conf
Logic Models Supporting the Design of MOBILE-based RTD Circuits.
ASAP
Maria J. Avedillo, José M. Quintana, Héctor Pettenghi
2004 — conf
Programmable logic gate based on resonant tunnelling devices.
ISCAS (3)
José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
2004 B conf
RTD-based compact programmable gates.
IJCNN
José M. Quintana, Maria J. Avedillo, Héctor Pettenghi