Hyunsu Chae - RankMe

13 papers A* 1A 3B 1Journal 2Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Invited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to Layout. ICCAD Hyunsu Chae, Seunggeun Kim, Souradip Poddar, Xiaohan Gao, Sensen Li, David Z. Pan
2025	—	`conf`	ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA. ASP-DAC Hyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan
2024	J	`jnl`	A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. IEEE J. Solid State Circuits Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Jisu Yook, Jihoon Lee, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sungsik Park, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim, Sung-Ung Kwak
2024	J	`jnl`	ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2024	B	`conf`	ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. ASPDAC Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan
2024	A	`conf`	PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design. ICCAD Hyunsu Chae, Hao Yu, Sensen Li, David Z. Pan
2023	—	`conf`	A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. ISSCC Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim
2023	A	`conf`	ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. DATE Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2022	—	`conf`	A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. ESSCIRC Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee
2018	A*	`conf`	Test cost reduction for DAC Hyunsu Chae, Joon-Sung Yang
2005	—	`conf`	A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology. ISWCS Hyunsu Chae, Eun-Chul Park, Choong-Yul Cha, Jungeun Lee, Chun-Deok Suh, Jeongwook Koh, Hanseung Lee, Hoon-Tae Kim
2004	—	`conf`	An improved architecture of the mixed mode clock/data recovery for DVD read channel. CICC Jungeun Lee, Hyunsu Chae, Hanseung Lee, Maxim Konakov, Junghyun Lee, Jeongwon Lee
2004	—	`conf`	High speed mixed analog/digital PRML architecture for optical data storage system. SoCC Maxim Konakov, Jae-Wook Lee, Junghyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee