Hyunjin Lee

11 papers A* 3B 1C 1Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2011 A* conf
CloudCache: Expanding and shrinking private caches.
HPCA
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2011 J jnl
DEFCAM: A design and evaluation framework for defect-tolerant cache memories.
ACM Trans. Archit. Code Optim.
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2010 J jnl
PERFECTORY: A Fault-Tolerant Directory Memory Architecture.
IEEE Trans. Computers
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2010 A* conf
StimulusCache: Boosting performance of chip multiprocessors with excess cache.
HPCA
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2010 J jnl
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach.
Softw. Pract. Exp.
Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho
2009 — conf
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor.
ISVLSI
Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho
2009 A* conf
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.
MICRO
Sangyeun Cho, Hyunjin Lee
2008 B conf
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation.
ICPP
Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng
2007 C conf
Exploring the interplay of yield, area, and performance in processor caches.
ICCD
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2007 — conf
Performance of Graceful Degradation for Cache Faults.
ISVLSI
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2006 — conf
A flexible data to L2 cache mapping approach for future multicore processors.
Memory System Performance and Correctness
Lei Jin, Hyunjin Lee, Sangyeun Cho