Hyungsoo Kim

18 papers B 1C 1Misc 1Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2026 — conf
15.9 A 48Gb/s 24Gb GDDR7 DRAM for Mid-Range Inference AI with Symmetric 2CH-Mode Operation, Clock-Path Optimization, and RAS Features.
ISSCC
Hyunsu Park, Sungkwon Lee, Kyunghoon Kim, Jin-Youp Cha, Hyeongjun Ko, Jaehyeok Yang, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Jiseok Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Seulgi Kim, Eunji Song, Junghwan Ji, Byungjun Kang, Boram Kim, Sang-Yeon Byeon, Hankyu Chi, Hyungsoo Kim, Jonghwan Kim
2026 — conf
A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode.
ISSCC
Jungtaek You, Mino Kim, Dae-Han Kwon, SangSic Yoon, Joonhong Park, Hyungrok Do, Jeongje Park, Yooseok Jung, Seongseop Lee, Kyuyoung Kim, Hyeongsoo Jeong, Jaeyeol Kang, Hanbyeol Kwon, Minwook Oh, Jieun Kim, Jinseok Oh, Gi-Moon Hong, Dongyoon Ka, Seungho Lee, Heewoong Song, Minchang Kim, Daeho Yun, Sooncheol Kwon, Dongbeom Lee, Taekyun Shin, Jongmyeong Lee, Jungmin Yoon, Kyeong Pil Kang, Sanghyuk Heo, Dongkyun Kim, Jieun Jang, Hyungsoo Kim
2023 — conf
System Optimization of Data Analytics Platforms using Compute Express Link (CXL) Memory.
BigComp
Seokhyun Ryu, Sohyun Kim, Jaeyung Jun, Donguk Moon, Kyungsoo Lee, Jungmin Choi, Sunwoong Kim, Hyungsoo Kim, Luke Kim, Won Ha Choi, Moohyeon Nam, Dooyoung Hwang, Hongchan Roh, Young-Pyo Joo
2022 J jnl
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits
Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha
2022 Misc conf
Quality of Service Evaluation over a 496 km Quantum Key Distribution Network.
SoftCOM
Miryeong Park, Kyungwoon Lee, Kanghee Seol, Minsoo Lee, Hyungsoo Kim
2021 J jnl
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim
2021 — conf
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
ISSCC
Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha
2021 — conf
Design and Implementation of Quantum Key Distribution Network Control and Management.
ICTC
Taesang Choi, Sangsik Yoon, Taeyeon Kim, Hyungsoo Kim
2017 — conf
23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4.
ISSCC
Woojun Choi, Taewoong Kim, Jongjoo Shim, Hyungsoo Kim, Gunhee Han, Youngcheol Chae
2015 — conf
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications.
VLSIC
Hae-Kang Jung, Jaemo Yang, Jeonghun Lee, Hyeongjun Ko, Hyuk Lee, Taeksang Song, Jongjoo Shim, Sangkwon Lee, Keunsoo Song, Dongkyun Kim, Hyungsoo Kim, Yunsaing Kim
2015 — conf
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.
3DIC
Sumin Choi, Heegon Kim, Daniel H. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim
2012 — conf
A 1.2V 23nm 6F
ISSCC
Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong
2012 — conf
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
ISSCC
Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, HyeYoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim
2012 C conf
Energy/carbon management network for IT equipments.
APNOMS
Sungbong Chang, Hyungsoo Kim, ByungDeok Chung, Hyunchul Jung
2009 B conf
Efficient transmit antenna selection for correlated MIMO channels.
WCNC
Hyungsoo Kim, Hyounkuk Kim, Namshik Kim, Hyuncheol Park, Seok Seo, Jin-Kyu Choi
2008 J jnl
Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network.
IEICE Trans. Electron.
Hyunjeong Park, Hyungsoo Kim, Junso Pak, Changwook Yoon, Kyoungchoul Koo, Joungho Kim
2006 J jnl
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.
IEEE J. Solid State Circuits
Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jinhan Kim, Kicheol Bae, Jiheon Yu, Hoi-Jun Yoo, Joungho Kim
2005 — conf
Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB.
ISCAS (6)
Joungho Kim, Junso Pak, Jongbae Park, Hyungsoo Kim