Hyungil Chae

21 papers C 1Journal 14Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Design Approaches for Efficient Parallel Pseudo-Random Ternary Sequence Generation.
IEEE Trans. Circuits Syst. I Regul. Pap.
DongKwon Lee, Hyungil Chae, Jintae Kim, Dongsuk Jeon
2025 J jnl
A 17-fJ/conv-step FoM
IEEE Trans. Circuits Syst. II Express Briefs
JunMin Park, Joonhyun Park, Seungjun Song, Hyungil Chae
2025 C conf
A 389μm
ISCAS
Kyungmin Lee, Seungjun Song, Hyungil Chae
2024 J jnl
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method.
IEEE J. Solid State Circuits
Jonghyun Kim, Hyungil Chae
2024 J jnl
A 150-MS/s, 65-dB SNDR Fully Passive Bandpass Noise-Shaping SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Dongsik Lee, Seungjun Lee, Hyungil Chae
2024 — conf
A 50MHz-BW 168.8dB-FoM 2x Time-Interleaved Bandpass Noise Shaping SAR ADC Using Passive Filter.
CICC
Seungjun Song, Dongsik Lee, Hyungil Chae
2024 — conf
An 8-bit 20.2fJ/conv-step FoM CI-C Asynchronous SAR ADC with Common-mode Level Shifting.
A-SSCC
Seungjun Song, Kyungmin Lee, Hyungil Chae
2023 J jnl
A 3.68 aF
IEEE J. Solid State Circuits
Sujin Park, Hyungil Chae, SeongHwan Cho
2023 J jnl
A 600-MS/s, 65-dB SNDR, 75-MHz BW Time-Interleaved Noise-Shaping SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Jihyun Baek, Hyungil Chae
2021 — conf
A 3.68aFrms Resolution 183dB FoMs 4
VLSI Circuits
Sujin Park, Hyungil Chae, SeongHwan Cho
2021 J jnl
A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration.
IEEE Access
Jae Sik Yoon, Jiyoon Hong, Hyungil Chae, Jintae Kim
2021 J jnl
An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure.
IEEE J. Solid State Circuits
Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
2021 J jnl
Readout Integrated Circuit for Small-Sized and Low-Power Gas Sensor Based on HEMT Device.
Sensors
Seungjun Lee, Joohwan Jin, Jihyun Baek, Juyong Lee, Hyungil Chae
2020 — conf
A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1-2 MASH structure.
CICC
Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
2020 — conf
Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited).
CICC
Michael P. Flynn, Jaehun Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell
2020 J jnl
Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC.
Sensors
Juyoung Lee, Younggyun Oh, Sein Oh, Hyungil Chae
2019 J jnl
4-Contact structure of vertical-type CMOS Hall device for 3-D magnetic sensor.
IEICE Electron. Express
Sein Oh, Dong-young Hwang, Hyungil Chae
2017 J jnl
Double-sampling highpass delta-sigma modulator with inherent frequency translation.
IEICE Electron. Express
Hyungil Chae
2016 J jnl
A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability.
IEEE J. Solid State Circuits
Hyungil Chae, Michael P. Flynn
2014 J jnl
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF.
IEEE J. Solid State Circuits
Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
2012 — conf
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF.
ISSCC
Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn