Hyun J. Shin - RankMe

13 papers Journal 13

Year	Rank	Type	Title / Venue / Authors
2004	J	`jnl`	A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. IEEE J. Solid State Circuits Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong
1999	J	`jnl`	Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
1996	J	`jnl`	Single-chip 4×500-MBd CMOS transceiver. IEEE J. Solid State Circuits Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin
1995	J	`jnl`	Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications. IBM J. Res. Dev. Hyun J. Shin, Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner
1995	J	`jnl`	Digital FIR filters for high speed PRML disk read channels. IEEE J. Solid State Circuits Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner, Michael Immediato, Richard L. Galbraith, Hyun J. Shin
1994	J	`jnl`	A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits. IEEE J. Solid State Circuits Hyun J. Shin
1993	J	`jnl`	High-speed low-power Darlington ECL circuit. IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin, Pong-Fei Lu, Hyun J. Shin
1992	J	`jnl`	An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch. IEEE J. Solid State Circuits Hyun J. Shin, Michael Immediato
1992	J	`jnl`	High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage. IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin, Hyun J. Shin, Pong-Fei Lu
1991	J	`jnl`	A high-speed low-power JFET pull-down ECL circuit. IEEE J. Solid State Circuits Hyun J. Shin, Pong-Fei Lu, Ching-Te Chuang
1991	J	`jnl`	Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration. IEEE J. Solid State Circuits Hyun J. Shin
1990	J	`jnl`	Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits. IEEE J. Solid State Circuits Hyun J. Shin
1989	J	`jnl`	A 250-Mbit/s CMOS crosspoint switch. IEEE J. Solid State Circuits Hyun J. Shin, David A. Hodges