Hyun-Kyu Yu

17 papers C 1Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2014 — conf
A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm.
MWSCAS
Ja-Yol Lee, Mi-Jeong Park, Hyun-Kyu Yu, Cheon-Soo Kim
2013 J jnl
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.
IET Circuits Devices Syst.
Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu
2012 J jnl
A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu
2011 — conf
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS.
ISSCC
Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho
2011 — conf
A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip.
ESSCIRC
Hoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Yun Seong Eo, Hyun-Kyu Yu
2008 J jnl
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology.
IEEE J. Solid State Circuits
Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu
2006 J jnl
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.
IEEE J. Solid State Circuits
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
2006 — conf
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.
ISSCC
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
2006 — conf
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS.
ISSCC
Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu
2006 C conf
A transformer-based low phase noise and widely tuned CMOS quadrature VCO.
ISCAS
Young-Jae Lee, Hyun-Kyu Yu
2005 — conf
Automatic tuning circuit for Gm-C filters.
ICECS
Young-Ho Kim, Hyun-Kyu Yu
2004 — conf
A 1.8V triode-type transconductor and its application to a 10MHz 3
CICC
Young-Ho Kim, Jung-Woo Park, Mun-Yang Park, Hyun-Kyu Yu
2004 J jnl
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter.
IEEE J. Solid State Circuits
Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu
2004 J jnl
Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver.
IEEE J. Solid State Circuits
Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu
2002 — conf
A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA).
ISCAS (3)
Kwang-Jin Koh, Yong-Sik Youn, Hyun-Kyu Yu
2002 — conf
A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.
ISCAS (5)
Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
1999 J jnl
A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology.
IEEE Trans. Consumer Electron.
Keewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim