Hyun-Geun Byun

16 papers Journal 8Unranked 8

Year	Rank	Type	Title / Venue / Authors
2008	—	`conf`	A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. ISSCC Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim
2007	J	`jnl`	A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. IEEE J. Solid State Circuits Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, Kwangjin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Choong-Duk Ha, Ki-Sung Kim, Young-Ran Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim, YunSueng Shin
2006	—	`conf`	A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAM. ISSCC Sangbeom Kang, Wooyeong Cho, Beak-Hyung Cho, Kwangjin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Du-Eung Kim, Kang-Sik Cho, Choong-Duk Ha, Young-Ran Kim, Ki-Sung Kim, Choong-Ryeol Hwang, Choong-Keun Kwak, Hyun-Geun Byun, YunSueng Shin
2006	J	`jnl`	An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology. IEEE J. Solid State Circuits Kyomin Sohn, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo
2006	J	`jnl`	Enhanced write performance of a 64-mb phase-change random access memory. IEEE J. Solid State Circuits Hyung-Rok Oh, Beak-Hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hye-Jin Kim, Ki-Sung Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim
2005	J	`jnl`	A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM). IEEE J. Solid State Circuits Woo Yeong Cho, Beak-Hyung Cho, Byung-Gil Choi, Hyung-Rok Oh, Sangbeom Kang, Ki-Sung Kim, Kyung-Hee Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Youngnam Hwang, Sujin Ahn, Gwan-Hyeob Koh, Gitae Jeong, Hongsik Jeong, Kinam Kim
2005	—	`conf`	A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. ISCAS (2) Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun
2005	J	`jnl`	A High Resolution, Wide Range Digital Impedance Controller. IEICE Trans. Electron. Tae-Hyoung Kim, Kwang-Jin Lee, Uk-Rae Cho, Hyun-Geun Byun
2005	J	`jnl`	A Low Jitter ADPLL for Mobile Applications. IEICE Trans. Electron. Kwang-Jin Lee, Hyo-Chang Kim, Uk-Rae Cho, Hyun-Geun Byun, Suki Kim
2005	—	`conf`	A pseudo-differential CMOS receiver insensitive to input common mode level. ISCAS (1) Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
2005	—	`conf`	Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. CICC Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
2004	—	`conf`	Modeling and Testing of Faults in TCAMs. AsiaSim Kwang-Jin Lee, Cheol Kim, Suki Kim, Uk-Rae Cho, Hyun-Geun Byun
2004	J	`jnl`	Synchronous mirror delay for multiphase locking. IEEE J. Solid State Circuits Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
2003	J	`jnl`	A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE J. Solid State Circuits Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun
2003	—	`conf`	New dynamic logic-level converters for high performance application. ISCAS (5) Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun
2003	—	`conf`	Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. CICC Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun