Hyeongjun Ko

12 papers C 1Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2026 — conf
15.9 A 48Gb/s 24Gb GDDR7 DRAM for Mid-Range Inference AI with Symmetric 2CH-Mode Operation, Clock-Path Optimization, and RAS Features.
ISSCC
Hyunsu Park, Sungkwon Lee, Kyunghoon Kim, Jin-Youp Cha, Hyeongjun Ko, Jaehyeok Yang, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Jiseok Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Seulgi Kim, Eunji Song, Junghwan Ji, Byungjun Kang, Boram Kim, Sang-Yeon Byeon, Hankyu Chi, Hyungsoo Kim, Jonghwan Kim
2025 — conf
22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces.
ISSCC
Boram Kim, Hankyu Chi, Hyeongjun Ko, Sang-Yeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jin-Youp Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
2024 — conf
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
ISSCC
Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jin-Youp Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sang-Yeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim
2024 J jnl
A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han
2021 J jnl
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer.
IEEE J. Solid State Circuits
Hyeongjun Ko, Mino Kim, Hyunkyu Park, Sangyoon Lee, Jaewook Kim, Suhwan Kim, Joo-Hyung Chae
2019 J jnl
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner.
IEEE Trans. Circuits Syst. II Express Briefs
Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim
2019 C conf
A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation.
ISCAS
Changho Hyun, Hyeongjun Ko, Joo-Hyung Chae, Hyunkyu Park, Suhwan Kim
2019 J jnl
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator.
IEEE Trans. Very Large Scale Integr. Syst.
Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim
2018 J jnl
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs
Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim
2017 — conf
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface.
ISOCC
Minchang Kim, Jihwan Park, Joo-Hyung Chae, Hyeongjun Ko, Mino Kim, Suhwan Kim
2015 — conf
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
A-SSCC
Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim
2015 — conf
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications.
VLSIC
Hae-Kang Jung, Jaemo Yang, Jeonghun Lee, Hyeongjun Ko, Hyuk Lee, Taeksang Song, Jongjoo Shim, Sangkwon Lee, Keunsoo Song, Dongkyun Kim, Hyungsoo Kim, Yunsaing Kim