Hyeong-Ju Kang

23 papers A* 2A 2Misc 1Journal 13Unranked 5
YearRankTypeTitle / Venue / Authors
2023 A conf
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture.
FPGA
Hyeong-Ju Kang
2023 J jnl
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning.
Sensors
Hyeong-Ju Kang, Byung-Do Yang
2022 J jnl
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture.
CoRR
Hyeong-Ju Kang
2020 J jnl
Accelerator-Aware Pruning for Convolutional Neural Networks.
IEEE Trans. Circuits Syst. Video Technol.
Hyeong-Ju Kang
2020 J jnl
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
2019 J jnl
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches.
IEEE Trans. Circuits Syst. II Express Briefs
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
2019 — conf
Real-Time Object Detection on 640x480 Image With VGG16+SSD.
FPT
Hyeong-Ju Kang
2019 J jnl
Short floating-point representation for convolutional neural network inference.
IEICE Electron. Express
Hyeong-Ju Kang
2018 J jnl
Accelerator-Aware Pruning for Convolutional Neural Networks.
CoRR
Hyeong-Ju Kang
2013 J jnl
Area-efficient convolutional deinterleaver for mobile TV receiver.
ACM Trans. Embed. Comput. Syst.
Hyeong-Ju Kang, Hee Suk Seo, Jin Kwak
2012 J jnl
Low-Power Time Deinterleaver for ISDB-T Receiver.
IEEE Trans. Circuits Syst. II Express Briefs
Hyeong-Ju Kang, Byung-Do Yang
2011 J jnl
A Low Power Content Addressable Memory Using Low Swing Search Lines.
IEEE Trans. Circuits Syst. I Regul. Pap.
Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang
2011 J jnl
Area-Efficient Prefilter Architecture for a CDMA Receiver.
IEEE Trans. Circuits Syst. II Express Briefs
Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang
2005 — conf
A scalable SIMD digital signal processor for high-quality multifunctional printer systems.
Color Imaging: Processing, Hardcopy, and Applications
Hyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang
2005 J jnl
SAT-based unbounded symbolic model checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hyeong-Ju Kang, In-Cheol Park
2003 — conf
A 24-bit floating-point audio DSP controller supporting fast exponentiation.
ISCAS (2)
Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park
2003 — conf
Pairing and ordering to reduce hardware complexity in cascade form filter design.
ISCAS (4)
Hyeong-Ju Kang, In-Cheol Park
2003 A* conf
SAT-based unbounded symbolic model checking.
DAC
Hyeong-Ju Kang, In-Cheol Park
2002 Misc conf
A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure.
ICASSP
Hyeong-Ju Kang, In-Cheol Park
2002 J jnl
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
In-Cheol Park, Hyeong-Ju Kang
2001 A* conf
Digital Filter Synthesis Based on Minimal Signed Digit Representation.
DAC
In-Cheol Park, Hyeong-Ju Kang
2001 — conf
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.
ISCAS (2)
Hyeong-Ju Kang, In-Cheol Park
2000 A conf
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.
ICCAD
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park