Hyeok-Ki Hong

11 papers C 1Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
2020 C conf
A 62dB-SNDR 40.2μW 10MS/s ADC for Power Efficient IoT and Biomedical Read-Out Systems.
ISCAS
Hyeok-Ki Hong, Hyun-Wook Kang, Che-Heung Kim
2018 J jnl
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu
2018 J jnl
A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme.
IEEE J. Solid State Circuits
Hyun-Wook Kang, Hyeok-Ki Hong, Wan Kim, Seung-Tak Ryu
2017 J jnl
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dong-Jin Chang, Wan Kim, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu
2016 J jnl
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits
Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, Seung-Tak Ryu
2016 J jnl
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. II Express Briefs
Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu
2015 — conf
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.
ISSCC
Hyeok-Ki Hong, Hyun-Wook Kang, Dong-Shin Jo, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu
2015 J jnl
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC.
IEEE J. Solid State Circuits
Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu
2015 J jnl
Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs.
IEICE Electron. Express
Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn, Seung-Tak Ryu
2013 — conf
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement.
ISSCC
Hyeok-Ki Hong, Hyun-Wook Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu
2012 — conf
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control.
CICC
Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu