Hyein Lee

17 papers A* 3A 4Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2020 J jnl
Heuristic Methods for Fine-Grain Exploitation of FDSOI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
2019 J jnl
Enhancing sensitivity-based power reduction for an industry IC design context.
Integr.
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
2018 J jnl
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li
2018 — —
Physical Design and Technology Optimizations for Advanced VLSI Manufacturing
Hyein Lee
2017 J jnl
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2017 A conf
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.
ICCAD
Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu
2017 — conf
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes.
ISQED
Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang
2017 A* conf
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.
DAC
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2016 A conf
Measuring progress and value of IC implementation technology.
ICCAD
Andrew B. Kahng, Hyein Lee, Jiajia Li
2015 A* conf
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router.
DAC
Kwangsoo Han, Andrew B. Kahng, Hyein Lee
2015 A conf
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints.
ICCAD
Kwangsoo Han, Andrew B. Kahng, Hyein Lee
2014 — conf
Horizontal benchmark extension for improved assessment of physical CAD research.
ACM Great Lakes Symposium on VLSI
Andrew B. Kahng, Hyein Lee, Jiajia Li
2014 — conf
Minimum implant area-aware gate sizing and placement.
ACM Great Lakes Symposium on VLSI
Andrew B. Kahng, Hyein Lee
2014 — conf
Timing margin recovery with flexible flip-flop timing model.
ISQED
Andrew B. Kahng, Hyein Lee
2013 A conf
High-performance gate sizing with a signoff timer.
ICCAD
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar
2013 — conf
Learning-based approximation of interconnect delay and slew in signoff timing tools.
SLIP
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani
2013 A* conf
Smart non-default routing for clock power reduction.
DAC
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee