Hwang-Cherng Chow

19 papers Journal 5Unranked 14
YearRankTypeTitle / Venue / Authors
2022 — conf
Complex Human Activities Recognition Based on High Performance 1D CNN Model.
MCSoC
Raman Maurya, Tee Hui Teo, Shi Hui Chua, Hwang-Cherng Chow, I-Chyn Wey
2017 J jnl
A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect.
Sensors
Hwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng
2016 J jnl
Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application.
Sensors
Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng
2014 J jnl
Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits.
Int. J. Circuit Theory Appl.
I-Chyn Wey, Chien-Chang Peng, Hwang-Cherng Chow
2008 — conf
A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications.
DELTA
Hwang-Cherng Chow, Pu-Nan Weng
2008 — conf
A high performance peak detector sample and hold circuit for detecting power supply noise.
APCCAS
Hwang-Cherng Chow, Zhi-Hau Hor
2007 — conf
1V 10-bit successive approximation ADC for low power biomedical applications.
ECCTD
Hwang-Cherng Chow, Yi-Hung Chen
2007 — conf
High CMRR instrumentation amplifier for biomedical applications.
ISSPA
Hwang-Cherng Chow, Jia-Yu Wang
2005 — conf
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.
ISCAS (1)
Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng
2004 — conf
High performance sense amplifier circuit for low power SRAM applications.
ISCAS (2)
Hwang-Cherng Chow, Shu-Hsien Chang
2003 — conf
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.
ISCAS (5)
Hwang-Cherng Chow, I-Chyn Wey
2002 — conf
A 3.3 V 1 GHz high speed pipelined Booth multiplier.
ISCAS (1)
Hwang-Cherng Chow, I-Chyn Wey
2002 — conf
High performance automatic gain control circuit using a S/H peak-detector for ASK receiver.
ICECS
Hwang-Cherng Chow, I-Hsin Wang
2002 — conf
New pixel-shared design and split-path readout of CMOS image sensor circuits.
ISCAS (4)
Hwang-Cherng Chow, Yung-Kuo Ho
2000 — conf
Novel output buffer designs for universal serial bus IC applications.
ICECS
Hwang-Cherng Chow, Chen-Yi Huang, Chih-Hong Chang
1999 — conf
Bidirectional buffer for mixed voltage applications.
ISCAS (1)
Hwang-Cherng Chow
1999 — conf
Duty cycle control circuit and applications to frequency dividers.
ICECS
Hwang-Cherng Chow
1992 J jnl
An analytical CMOS inverter delay model including channel-length modulations.
IEEE J. Solid State Circuits
Hwang-Cherng Chow, Wu-Shiung Feng
1992 J jnl
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hwang-Cherng Chow, Wu-Shiung Feng, James B. Kuo